/**
 * \file IfxEvadc_bf.h
 * \brief
 * \copyright Copyright (c) 2019 Infineon Technologies AG. All rights reserved.
 *
 *
 * Version: TC38XA_UM_V1.1.0.R0
 * Specification: TC3xx User Manual V1.1.0
 * MAY BE CHANGED BY USER [yes/no]: No
 *
 *                                 IMPORTANT NOTICE
 *
 *
 * Use of this file is subject to the terms of use agreed between (i) you or 
 * the company in which ordinary course of business you are acting and (ii) 
 * Infineon Technologies AG or its licensees. If and as long as no such 
 * terms of use are agreed, use of this file is subject to following:


 * Boost Software License - Version 1.0 - August 17th, 2003

 * Permission is hereby granted, free of charge, to any person or 
 * organization obtaining a copy of the software and accompanying 
 * documentation covered by this license (the "Software") to use, reproduce,
 * display, distribute, execute, and transmit the Software, and to prepare
 * derivative works of the Software, and to permit third-parties to whom the 
 * Software is furnished to do so, all subject to the following:

 * The copyright notices in the Software and this entire statement, including
 * the above license grant, this restriction and the following disclaimer, must
 * be included in all copies of the Software, in whole or in part, and all
 * derivative works of the Software, unless such copies or derivative works are
 * solely in the form of machine-executable object code generated by a source
 * language processor.

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
 * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE 
 * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * \defgroup IfxSfr_Evadc_Registers_BitfieldsMask Bitfields mask and offset
 * \ingroup IfxSfr_Evadc_Registers
 * 
 */
#ifndef IFXEVADC_BF_H
#define IFXEVADC_BF_H 1

/******************************************************************************/

/******************************************************************************/

/** \addtogroup IfxSfr_Evadc_Registers_BitfieldsMask
 * \{  */
/** \brief Length for Ifx_EVADC_CLC_Bits.DISR */
#define IFX_EVADC_CLC_DISR_LEN (1u)

/** \brief Mask for Ifx_EVADC_CLC_Bits.DISR */
#define IFX_EVADC_CLC_DISR_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_CLC_Bits.DISR */
#define IFX_EVADC_CLC_DISR_OFF (0u)

/** \brief Length for Ifx_EVADC_CLC_Bits.DISS */
#define IFX_EVADC_CLC_DISS_LEN (1u)

/** \brief Mask for Ifx_EVADC_CLC_Bits.DISS */
#define IFX_EVADC_CLC_DISS_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_CLC_Bits.DISS */
#define IFX_EVADC_CLC_DISS_OFF (1u)

/** \brief Length for Ifx_EVADC_CLC_Bits.EDIS */
#define IFX_EVADC_CLC_EDIS_LEN (1u)

/** \brief Mask for Ifx_EVADC_CLC_Bits.EDIS */
#define IFX_EVADC_CLC_EDIS_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_CLC_Bits.EDIS */
#define IFX_EVADC_CLC_EDIS_OFF (3u)

/** \brief Length for Ifx_EVADC_ID_Bits.MOD_REV */
#define IFX_EVADC_ID_MOD_REV_LEN (8u)

/** \brief Mask for Ifx_EVADC_ID_Bits.MOD_REV */
#define IFX_EVADC_ID_MOD_REV_MSK (0xffu)

/** \brief Offset for Ifx_EVADC_ID_Bits.MOD_REV */
#define IFX_EVADC_ID_MOD_REV_OFF (0u)

/** \brief Length for Ifx_EVADC_ID_Bits.MOD_TYPE */
#define IFX_EVADC_ID_MOD_TYPE_LEN (8u)

/** \brief Mask for Ifx_EVADC_ID_Bits.MOD_TYPE */
#define IFX_EVADC_ID_MOD_TYPE_MSK (0xffu)

/** \brief Offset for Ifx_EVADC_ID_Bits.MOD_TYPE */
#define IFX_EVADC_ID_MOD_TYPE_OFF (8u)

/** \brief Length for Ifx_EVADC_ID_Bits.MOD_NUMBER */
#define IFX_EVADC_ID_MOD_NUMBER_LEN (16u)

/** \brief Mask for Ifx_EVADC_ID_Bits.MOD_NUMBER */
#define IFX_EVADC_ID_MOD_NUMBER_MSK (0xffffu)

/** \brief Offset for Ifx_EVADC_ID_Bits.MOD_NUMBER */
#define IFX_EVADC_ID_MOD_NUMBER_OFF (16u)

/** \brief Length for Ifx_EVADC_OCS_Bits.TGS */
#define IFX_EVADC_OCS_TGS_LEN (2u)

/** \brief Mask for Ifx_EVADC_OCS_Bits.TGS */
#define IFX_EVADC_OCS_TGS_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_OCS_Bits.TGS */
#define IFX_EVADC_OCS_TGS_OFF (0u)

/** \brief Length for Ifx_EVADC_OCS_Bits.TGB */
#define IFX_EVADC_OCS_TGB_LEN (1u)

/** \brief Mask for Ifx_EVADC_OCS_Bits.TGB */
#define IFX_EVADC_OCS_TGB_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_OCS_Bits.TGB */
#define IFX_EVADC_OCS_TGB_OFF (2u)

/** \brief Length for Ifx_EVADC_OCS_Bits.TG_P */
#define IFX_EVADC_OCS_TG_P_LEN (1u)

/** \brief Mask for Ifx_EVADC_OCS_Bits.TG_P */
#define IFX_EVADC_OCS_TG_P_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_OCS_Bits.TG_P */
#define IFX_EVADC_OCS_TG_P_OFF (3u)

/** \brief Length for Ifx_EVADC_OCS_Bits.SUS */
#define IFX_EVADC_OCS_SUS_LEN (4u)

/** \brief Mask for Ifx_EVADC_OCS_Bits.SUS */
#define IFX_EVADC_OCS_SUS_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_OCS_Bits.SUS */
#define IFX_EVADC_OCS_SUS_OFF (24u)

/** \brief Length for Ifx_EVADC_OCS_Bits.SUS_P */
#define IFX_EVADC_OCS_SUS_P_LEN (1u)

/** \brief Mask for Ifx_EVADC_OCS_Bits.SUS_P */
#define IFX_EVADC_OCS_SUS_P_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_OCS_Bits.SUS_P */
#define IFX_EVADC_OCS_SUS_P_OFF (28u)

/** \brief Length for Ifx_EVADC_OCS_Bits.SUSSTA */
#define IFX_EVADC_OCS_SUSSTA_LEN (1u)

/** \brief Mask for Ifx_EVADC_OCS_Bits.SUSSTA */
#define IFX_EVADC_OCS_SUSSTA_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_OCS_Bits.SUSSTA */
#define IFX_EVADC_OCS_SUSSTA_OFF (29u)

/** \brief Length for Ifx_EVADC_KRSTCLR_Bits.CLR */
#define IFX_EVADC_KRSTCLR_CLR_LEN (1u)

/** \brief Mask for Ifx_EVADC_KRSTCLR_Bits.CLR */
#define IFX_EVADC_KRSTCLR_CLR_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_KRSTCLR_Bits.CLR */
#define IFX_EVADC_KRSTCLR_CLR_OFF (0u)

/** \brief Length for Ifx_EVADC_KRST1_Bits.RST */
#define IFX_EVADC_KRST1_RST_LEN (1u)

/** \brief Mask for Ifx_EVADC_KRST1_Bits.RST */
#define IFX_EVADC_KRST1_RST_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_KRST1_Bits.RST */
#define IFX_EVADC_KRST1_RST_OFF (0u)

/** \brief Length for Ifx_EVADC_KRST0_Bits.RST */
#define IFX_EVADC_KRST0_RST_LEN (1u)

/** \brief Mask for Ifx_EVADC_KRST0_Bits.RST */
#define IFX_EVADC_KRST0_RST_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_KRST0_Bits.RST */
#define IFX_EVADC_KRST0_RST_OFF (0u)

/** \brief Length for Ifx_EVADC_KRST0_Bits.RSTSTAT */
#define IFX_EVADC_KRST0_RSTSTAT_LEN (1u)

/** \brief Mask for Ifx_EVADC_KRST0_Bits.RSTSTAT */
#define IFX_EVADC_KRST0_RSTSTAT_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_KRST0_Bits.RSTSTAT */
#define IFX_EVADC_KRST0_RSTSTAT_OFF (1u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN0 */
#define IFX_EVADC_ACCEN0_EN0_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN0 */
#define IFX_EVADC_ACCEN0_EN0_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN0 */
#define IFX_EVADC_ACCEN0_EN0_OFF (0u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN1 */
#define IFX_EVADC_ACCEN0_EN1_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN1 */
#define IFX_EVADC_ACCEN0_EN1_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN1 */
#define IFX_EVADC_ACCEN0_EN1_OFF (1u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN2 */
#define IFX_EVADC_ACCEN0_EN2_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN2 */
#define IFX_EVADC_ACCEN0_EN2_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN2 */
#define IFX_EVADC_ACCEN0_EN2_OFF (2u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN3 */
#define IFX_EVADC_ACCEN0_EN3_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN3 */
#define IFX_EVADC_ACCEN0_EN3_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN3 */
#define IFX_EVADC_ACCEN0_EN3_OFF (3u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN4 */
#define IFX_EVADC_ACCEN0_EN4_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN4 */
#define IFX_EVADC_ACCEN0_EN4_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN4 */
#define IFX_EVADC_ACCEN0_EN4_OFF (4u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN5 */
#define IFX_EVADC_ACCEN0_EN5_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN5 */
#define IFX_EVADC_ACCEN0_EN5_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN5 */
#define IFX_EVADC_ACCEN0_EN5_OFF (5u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN6 */
#define IFX_EVADC_ACCEN0_EN6_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN6 */
#define IFX_EVADC_ACCEN0_EN6_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN6 */
#define IFX_EVADC_ACCEN0_EN6_OFF (6u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN7 */
#define IFX_EVADC_ACCEN0_EN7_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN7 */
#define IFX_EVADC_ACCEN0_EN7_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN7 */
#define IFX_EVADC_ACCEN0_EN7_OFF (7u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN8 */
#define IFX_EVADC_ACCEN0_EN8_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN8 */
#define IFX_EVADC_ACCEN0_EN8_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN8 */
#define IFX_EVADC_ACCEN0_EN8_OFF (8u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN9 */
#define IFX_EVADC_ACCEN0_EN9_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN9 */
#define IFX_EVADC_ACCEN0_EN9_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN9 */
#define IFX_EVADC_ACCEN0_EN9_OFF (9u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN10 */
#define IFX_EVADC_ACCEN0_EN10_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN10 */
#define IFX_EVADC_ACCEN0_EN10_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN10 */
#define IFX_EVADC_ACCEN0_EN10_OFF (10u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN11 */
#define IFX_EVADC_ACCEN0_EN11_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN11 */
#define IFX_EVADC_ACCEN0_EN11_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN11 */
#define IFX_EVADC_ACCEN0_EN11_OFF (11u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN12 */
#define IFX_EVADC_ACCEN0_EN12_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN12 */
#define IFX_EVADC_ACCEN0_EN12_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN12 */
#define IFX_EVADC_ACCEN0_EN12_OFF (12u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN13 */
#define IFX_EVADC_ACCEN0_EN13_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN13 */
#define IFX_EVADC_ACCEN0_EN13_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN13 */
#define IFX_EVADC_ACCEN0_EN13_OFF (13u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN14 */
#define IFX_EVADC_ACCEN0_EN14_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN14 */
#define IFX_EVADC_ACCEN0_EN14_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN14 */
#define IFX_EVADC_ACCEN0_EN14_OFF (14u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN15 */
#define IFX_EVADC_ACCEN0_EN15_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN15 */
#define IFX_EVADC_ACCEN0_EN15_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN15 */
#define IFX_EVADC_ACCEN0_EN15_OFF (15u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN16 */
#define IFX_EVADC_ACCEN0_EN16_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN16 */
#define IFX_EVADC_ACCEN0_EN16_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN16 */
#define IFX_EVADC_ACCEN0_EN16_OFF (16u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN17 */
#define IFX_EVADC_ACCEN0_EN17_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN17 */
#define IFX_EVADC_ACCEN0_EN17_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN17 */
#define IFX_EVADC_ACCEN0_EN17_OFF (17u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN18 */
#define IFX_EVADC_ACCEN0_EN18_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN18 */
#define IFX_EVADC_ACCEN0_EN18_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN18 */
#define IFX_EVADC_ACCEN0_EN18_OFF (18u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN19 */
#define IFX_EVADC_ACCEN0_EN19_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN19 */
#define IFX_EVADC_ACCEN0_EN19_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN19 */
#define IFX_EVADC_ACCEN0_EN19_OFF (19u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN20 */
#define IFX_EVADC_ACCEN0_EN20_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN20 */
#define IFX_EVADC_ACCEN0_EN20_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN20 */
#define IFX_EVADC_ACCEN0_EN20_OFF (20u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN21 */
#define IFX_EVADC_ACCEN0_EN21_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN21 */
#define IFX_EVADC_ACCEN0_EN21_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN21 */
#define IFX_EVADC_ACCEN0_EN21_OFF (21u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN22 */
#define IFX_EVADC_ACCEN0_EN22_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN22 */
#define IFX_EVADC_ACCEN0_EN22_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN22 */
#define IFX_EVADC_ACCEN0_EN22_OFF (22u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN23 */
#define IFX_EVADC_ACCEN0_EN23_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN23 */
#define IFX_EVADC_ACCEN0_EN23_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN23 */
#define IFX_EVADC_ACCEN0_EN23_OFF (23u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN24 */
#define IFX_EVADC_ACCEN0_EN24_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN24 */
#define IFX_EVADC_ACCEN0_EN24_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN24 */
#define IFX_EVADC_ACCEN0_EN24_OFF (24u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN25 */
#define IFX_EVADC_ACCEN0_EN25_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN25 */
#define IFX_EVADC_ACCEN0_EN25_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN25 */
#define IFX_EVADC_ACCEN0_EN25_OFF (25u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN26 */
#define IFX_EVADC_ACCEN0_EN26_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN26 */
#define IFX_EVADC_ACCEN0_EN26_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN26 */
#define IFX_EVADC_ACCEN0_EN26_OFF (26u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN27 */
#define IFX_EVADC_ACCEN0_EN27_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN27 */
#define IFX_EVADC_ACCEN0_EN27_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN27 */
#define IFX_EVADC_ACCEN0_EN27_OFF (27u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN28 */
#define IFX_EVADC_ACCEN0_EN28_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN28 */
#define IFX_EVADC_ACCEN0_EN28_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN28 */
#define IFX_EVADC_ACCEN0_EN28_OFF (28u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN29 */
#define IFX_EVADC_ACCEN0_EN29_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN29 */
#define IFX_EVADC_ACCEN0_EN29_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN29 */
#define IFX_EVADC_ACCEN0_EN29_OFF (29u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN30 */
#define IFX_EVADC_ACCEN0_EN30_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN30 */
#define IFX_EVADC_ACCEN0_EN30_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN30 */
#define IFX_EVADC_ACCEN0_EN30_OFF (30u)

/** \brief Length for Ifx_EVADC_ACCEN0_Bits.EN31 */
#define IFX_EVADC_ACCEN0_EN31_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCEN0_Bits.EN31 */
#define IFX_EVADC_ACCEN0_EN31_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCEN0_Bits.EN31 */
#define IFX_EVADC_ACCEN0_EN31_OFF (31u)

/** \brief Length for Ifx_EVADC_GLOBCFG_Bits.USC */
#define IFX_EVADC_GLOBCFG_USC_LEN (1u)

/** \brief Mask for Ifx_EVADC_GLOBCFG_Bits.USC */
#define IFX_EVADC_GLOBCFG_USC_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_GLOBCFG_Bits.USC */
#define IFX_EVADC_GLOBCFG_USC_OFF (12u)

/** \brief Length for Ifx_EVADC_GLOBCFG_Bits.SUPLEV */
#define IFX_EVADC_GLOBCFG_SUPLEV_LEN (2u)

/** \brief Mask for Ifx_EVADC_GLOBCFG_Bits.SUPLEV */
#define IFX_EVADC_GLOBCFG_SUPLEV_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_GLOBCFG_Bits.SUPLEV */
#define IFX_EVADC_GLOBCFG_SUPLEV_OFF (13u)

/** \brief Length for Ifx_EVADC_GLOBCFG_Bits.CPWC */
#define IFX_EVADC_GLOBCFG_CPWC_LEN (1u)

/** \brief Mask for Ifx_EVADC_GLOBCFG_Bits.CPWC */
#define IFX_EVADC_GLOBCFG_CPWC_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_GLOBCFG_Bits.CPWC */
#define IFX_EVADC_GLOBCFG_CPWC_OFF (15u)

/** \brief Length for Ifx_EVADC_GLOBCFG_Bits.SUCAL */
#define IFX_EVADC_GLOBCFG_SUCAL_LEN (1u)

/** \brief Mask for Ifx_EVADC_GLOBCFG_Bits.SUCAL */
#define IFX_EVADC_GLOBCFG_SUCAL_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_GLOBCFG_Bits.SUCAL */
#define IFX_EVADC_GLOBCFG_SUCAL_OFF (31u)

/** \brief Length for Ifx_EVADC_ACCPROT0_Bits.APCP */
#define IFX_EVADC_ACCPROT0_APCP_LEN (8u)

/** \brief Mask for Ifx_EVADC_ACCPROT0_Bits.APCP */
#define IFX_EVADC_ACCPROT0_APCP_MSK (0xffu)

/** \brief Offset for Ifx_EVADC_ACCPROT0_Bits.APCP */
#define IFX_EVADC_ACCPROT0_APCP_OFF (0u)

/** \brief Length for Ifx_EVADC_ACCPROT0_Bits.APCS */
#define IFX_EVADC_ACCPROT0_APCS_LEN (4u)

/** \brief Mask for Ifx_EVADC_ACCPROT0_Bits.APCS */
#define IFX_EVADC_ACCPROT0_APCS_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_ACCPROT0_Bits.APCS */
#define IFX_EVADC_ACCPROT0_APCS_OFF (8u)

/** \brief Length for Ifx_EVADC_ACCPROT0_Bits.APIP */
#define IFX_EVADC_ACCPROT0_APIP_LEN (8u)

/** \brief Mask for Ifx_EVADC_ACCPROT0_Bits.APIP */
#define IFX_EVADC_ACCPROT0_APIP_MSK (0xffu)

/** \brief Offset for Ifx_EVADC_ACCPROT0_Bits.APIP */
#define IFX_EVADC_ACCPROT0_APIP_OFF (16u)

/** \brief Length for Ifx_EVADC_ACCPROT0_Bits.APIS */
#define IFX_EVADC_ACCPROT0_APIS_LEN (4u)

/** \brief Mask for Ifx_EVADC_ACCPROT0_Bits.APIS */
#define IFX_EVADC_ACCPROT0_APIS_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_ACCPROT0_Bits.APIS */
#define IFX_EVADC_ACCPROT0_APIS_OFF (24u)

/** \brief Length for Ifx_EVADC_ACCPROT1_Bits.APSP */
#define IFX_EVADC_ACCPROT1_APSP_LEN (8u)

/** \brief Mask for Ifx_EVADC_ACCPROT1_Bits.APSP */
#define IFX_EVADC_ACCPROT1_APSP_MSK (0xffu)

/** \brief Offset for Ifx_EVADC_ACCPROT1_Bits.APSP */
#define IFX_EVADC_ACCPROT1_APSP_OFF (0u)

/** \brief Length for Ifx_EVADC_ACCPROT1_Bits.APSS */
#define IFX_EVADC_ACCPROT1_APSS_LEN (4u)

/** \brief Mask for Ifx_EVADC_ACCPROT1_Bits.APSS */
#define IFX_EVADC_ACCPROT1_APSS_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_ACCPROT1_Bits.APSS */
#define IFX_EVADC_ACCPROT1_APSS_OFF (8u)

/** \brief Length for Ifx_EVADC_ACCPROT1_Bits.APRP */
#define IFX_EVADC_ACCPROT1_APRP_LEN (8u)

/** \brief Mask for Ifx_EVADC_ACCPROT1_Bits.APRP */
#define IFX_EVADC_ACCPROT1_APRP_MSK (0xffu)

/** \brief Offset for Ifx_EVADC_ACCPROT1_Bits.APRP */
#define IFX_EVADC_ACCPROT1_APRP_OFF (16u)

/** \brief Length for Ifx_EVADC_ACCPROT1_Bits.APRS */
#define IFX_EVADC_ACCPROT1_APRS_LEN (4u)

/** \brief Mask for Ifx_EVADC_ACCPROT1_Bits.APRS */
#define IFX_EVADC_ACCPROT1_APRS_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_ACCPROT1_Bits.APRS */
#define IFX_EVADC_ACCPROT1_APRS_OFF (24u)

/** \brief Length for Ifx_EVADC_ACCPROT2_Bits.APF */
#define IFX_EVADC_ACCPROT2_APF_LEN (4u)

/** \brief Mask for Ifx_EVADC_ACCPROT2_Bits.APF */
#define IFX_EVADC_ACCPROT2_APF_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_ACCPROT2_Bits.APF */
#define IFX_EVADC_ACCPROT2_APF_OFF (0u)

/** \brief Length for Ifx_EVADC_ACCPROT2_Bits.APGC */
#define IFX_EVADC_ACCPROT2_APGC_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCPROT2_Bits.APGC */
#define IFX_EVADC_ACCPROT2_APGC_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCPROT2_Bits.APGC */
#define IFX_EVADC_ACCPROT2_APGC_OFF (16u)

/** \brief Length for Ifx_EVADC_ACCPROT2_Bits.APEM */
#define IFX_EVADC_ACCPROT2_APEM_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCPROT2_Bits.APEM */
#define IFX_EVADC_ACCPROT2_APEM_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCPROT2_Bits.APEM */
#define IFX_EVADC_ACCPROT2_APEM_OFF (17u)

/** \brief Length for Ifx_EVADC_ACCPROT2_Bits.APTF */
#define IFX_EVADC_ACCPROT2_APTF_LEN (1u)

/** \brief Mask for Ifx_EVADC_ACCPROT2_Bits.APTF */
#define IFX_EVADC_ACCPROT2_APTF_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_ACCPROT2_Bits.APTF */
#define IFX_EVADC_ACCPROT2_APTF_OFF (18u)

/** \brief Length for Ifx_EVADC_GLOB_ICLASS_Bits.STCS */
#define IFX_EVADC_GLOB_ICLASS_STCS_LEN (5u)

/** \brief Mask for Ifx_EVADC_GLOB_ICLASS_Bits.STCS */
#define IFX_EVADC_GLOB_ICLASS_STCS_MSK (0x1fu)

/** \brief Offset for Ifx_EVADC_GLOB_ICLASS_Bits.STCS */
#define IFX_EVADC_GLOB_ICLASS_STCS_OFF (0u)

/** \brief Length for Ifx_EVADC_GLOB_ICLASS_Bits.AIPS */
#define IFX_EVADC_GLOB_ICLASS_AIPS_LEN (2u)

/** \brief Mask for Ifx_EVADC_GLOB_ICLASS_Bits.AIPS */
#define IFX_EVADC_GLOB_ICLASS_AIPS_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_GLOB_ICLASS_Bits.AIPS */
#define IFX_EVADC_GLOB_ICLASS_AIPS_OFF (6u)

/** \brief Length for Ifx_EVADC_GLOB_ICLASS_Bits.CMS */
#define IFX_EVADC_GLOB_ICLASS_CMS_LEN (2u)

/** \brief Mask for Ifx_EVADC_GLOB_ICLASS_Bits.CMS */
#define IFX_EVADC_GLOB_ICLASS_CMS_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_GLOB_ICLASS_Bits.CMS */
#define IFX_EVADC_GLOB_ICLASS_CMS_OFF (8u)

/** \brief Length for Ifx_EVADC_GLOB_ICLASS_Bits.SESPS */
#define IFX_EVADC_GLOB_ICLASS_SESPS_LEN (1u)

/** \brief Mask for Ifx_EVADC_GLOB_ICLASS_Bits.SESPS */
#define IFX_EVADC_GLOB_ICLASS_SESPS_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_GLOB_ICLASS_Bits.SESPS */
#define IFX_EVADC_GLOB_ICLASS_SESPS_OFF (10u)

/** \brief Length for Ifx_EVADC_GLOB_ICLASS_Bits.STCE */
#define IFX_EVADC_GLOB_ICLASS_STCE_LEN (5u)

/** \brief Mask for Ifx_EVADC_GLOB_ICLASS_Bits.STCE */
#define IFX_EVADC_GLOB_ICLASS_STCE_MSK (0x1fu)

/** \brief Offset for Ifx_EVADC_GLOB_ICLASS_Bits.STCE */
#define IFX_EVADC_GLOB_ICLASS_STCE_OFF (16u)

/** \brief Length for Ifx_EVADC_GLOB_ICLASS_Bits.AIPE */
#define IFX_EVADC_GLOB_ICLASS_AIPE_LEN (2u)

/** \brief Mask for Ifx_EVADC_GLOB_ICLASS_Bits.AIPE */
#define IFX_EVADC_GLOB_ICLASS_AIPE_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_GLOB_ICLASS_Bits.AIPE */
#define IFX_EVADC_GLOB_ICLASS_AIPE_OFF (22u)

/** \brief Length for Ifx_EVADC_GLOB_ICLASS_Bits.CME */
#define IFX_EVADC_GLOB_ICLASS_CME_LEN (2u)

/** \brief Mask for Ifx_EVADC_GLOB_ICLASS_Bits.CME */
#define IFX_EVADC_GLOB_ICLASS_CME_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_GLOB_ICLASS_Bits.CME */
#define IFX_EVADC_GLOB_ICLASS_CME_OFF (24u)

/** \brief Length for Ifx_EVADC_GLOB_ICLASS_Bits.SESPE */
#define IFX_EVADC_GLOB_ICLASS_SESPE_LEN (1u)

/** \brief Mask for Ifx_EVADC_GLOB_ICLASS_Bits.SESPE */
#define IFX_EVADC_GLOB_ICLASS_SESPE_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_GLOB_ICLASS_Bits.SESPE */
#define IFX_EVADC_GLOB_ICLASS_SESPE_OFF (26u)

/** \brief Length for Ifx_EVADC_GLOB_BOUND_Bits.BOUNDARY0 */
#define IFX_EVADC_GLOB_BOUND_BOUNDARY0_LEN (12u)

/** \brief Mask for Ifx_EVADC_GLOB_BOUND_Bits.BOUNDARY0 */
#define IFX_EVADC_GLOB_BOUND_BOUNDARY0_MSK (0xfffu)

/** \brief Offset for Ifx_EVADC_GLOB_BOUND_Bits.BOUNDARY0 */
#define IFX_EVADC_GLOB_BOUND_BOUNDARY0_OFF (0u)

/** \brief Length for Ifx_EVADC_GLOB_BOUND_Bits.BOUNDARY1 */
#define IFX_EVADC_GLOB_BOUND_BOUNDARY1_LEN (12u)

/** \brief Mask for Ifx_EVADC_GLOB_BOUND_Bits.BOUNDARY1 */
#define IFX_EVADC_GLOB_BOUND_BOUNDARY1_MSK (0xfffu)

/** \brief Offset for Ifx_EVADC_GLOB_BOUND_Bits.BOUNDARY1 */
#define IFX_EVADC_GLOB_BOUND_BOUNDARY1_OFF (16u)

/** \brief Length for Ifx_EVADC_GLOB_EFLAG_Bits.REVGLB */
#define IFX_EVADC_GLOB_EFLAG_REVGLB_LEN (1u)

/** \brief Mask for Ifx_EVADC_GLOB_EFLAG_Bits.REVGLB */
#define IFX_EVADC_GLOB_EFLAG_REVGLB_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_GLOB_EFLAG_Bits.REVGLB */
#define IFX_EVADC_GLOB_EFLAG_REVGLB_OFF (8u)

/** \brief Length for Ifx_EVADC_GLOB_EFLAG_Bits.REVGLBCLR */
#define IFX_EVADC_GLOB_EFLAG_REVGLBCLR_LEN (1u)

/** \brief Mask for Ifx_EVADC_GLOB_EFLAG_Bits.REVGLBCLR */
#define IFX_EVADC_GLOB_EFLAG_REVGLBCLR_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_GLOB_EFLAG_Bits.REVGLBCLR */
#define IFX_EVADC_GLOB_EFLAG_REVGLBCLR_OFF (24u)

/** \brief Length for Ifx_EVADC_GLOB_EVNP_Bits.REV0NP */
#define IFX_EVADC_GLOB_EVNP_REV0NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_GLOB_EVNP_Bits.REV0NP */
#define IFX_EVADC_GLOB_EVNP_REV0NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_GLOB_EVNP_Bits.REV0NP */
#define IFX_EVADC_GLOB_EVNP_REV0NP_OFF (16u)

/** \brief Length for Ifx_EVADC_GLOB_TF_Bits.CDCH */
#define IFX_EVADC_GLOB_TF_CDCH_LEN (4u)

/** \brief Mask for Ifx_EVADC_GLOB_TF_Bits.CDCH */
#define IFX_EVADC_GLOB_TF_CDCH_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_GLOB_TF_Bits.CDCH */
#define IFX_EVADC_GLOB_TF_CDCH_OFF (0u)

/** \brief Length for Ifx_EVADC_GLOB_TF_Bits.CDGR */
#define IFX_EVADC_GLOB_TF_CDGR_LEN (4u)

/** \brief Mask for Ifx_EVADC_GLOB_TF_Bits.CDGR */
#define IFX_EVADC_GLOB_TF_CDGR_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_GLOB_TF_Bits.CDGR */
#define IFX_EVADC_GLOB_TF_CDGR_OFF (4u)

/** \brief Length for Ifx_EVADC_GLOB_TF_Bits.CDEN */
#define IFX_EVADC_GLOB_TF_CDEN_LEN (1u)

/** \brief Mask for Ifx_EVADC_GLOB_TF_Bits.CDEN */
#define IFX_EVADC_GLOB_TF_CDEN_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_GLOB_TF_Bits.CDEN */
#define IFX_EVADC_GLOB_TF_CDEN_OFF (8u)

/** \brief Length for Ifx_EVADC_GLOB_TF_Bits.CDSEL */
#define IFX_EVADC_GLOB_TF_CDSEL_LEN (2u)

/** \brief Mask for Ifx_EVADC_GLOB_TF_Bits.CDSEL */
#define IFX_EVADC_GLOB_TF_CDSEL_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_GLOB_TF_Bits.CDSEL */
#define IFX_EVADC_GLOB_TF_CDSEL_OFF (9u)

/** \brief Length for Ifx_EVADC_GLOB_TF_Bits.CDWC */
#define IFX_EVADC_GLOB_TF_CDWC_LEN (1u)

/** \brief Mask for Ifx_EVADC_GLOB_TF_Bits.CDWC */
#define IFX_EVADC_GLOB_TF_CDWC_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_GLOB_TF_Bits.CDWC */
#define IFX_EVADC_GLOB_TF_CDWC_OFF (15u)

/** \brief Length for Ifx_EVADC_GLOB_TF_Bits.PDD */
#define IFX_EVADC_GLOB_TF_PDD_LEN (1u)

/** \brief Mask for Ifx_EVADC_GLOB_TF_Bits.PDD */
#define IFX_EVADC_GLOB_TF_PDD_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_GLOB_TF_Bits.PDD */
#define IFX_EVADC_GLOB_TF_PDD_OFF (16u)

/** \brief Length for Ifx_EVADC_GLOB_TF_Bits.MDPD */
#define IFX_EVADC_GLOB_TF_MDPD_LEN (1u)

/** \brief Mask for Ifx_EVADC_GLOB_TF_Bits.MDPD */
#define IFX_EVADC_GLOB_TF_MDPD_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_GLOB_TF_Bits.MDPD */
#define IFX_EVADC_GLOB_TF_MDPD_OFF (17u)

/** \brief Length for Ifx_EVADC_GLOB_TF_Bits.MDPU */
#define IFX_EVADC_GLOB_TF_MDPU_LEN (1u)

/** \brief Mask for Ifx_EVADC_GLOB_TF_Bits.MDPU */
#define IFX_EVADC_GLOB_TF_MDPU_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_GLOB_TF_Bits.MDPU */
#define IFX_EVADC_GLOB_TF_MDPU_OFF (18u)

/** \brief Length for Ifx_EVADC_GLOB_TF_Bits.MDWC */
#define IFX_EVADC_GLOB_TF_MDWC_LEN (1u)

/** \brief Mask for Ifx_EVADC_GLOB_TF_Bits.MDWC */
#define IFX_EVADC_GLOB_TF_MDWC_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_GLOB_TF_Bits.MDWC */
#define IFX_EVADC_GLOB_TF_MDWC_OFF (23u)

/** \brief Length for Ifx_EVADC_GLOB_TE_Bits.TFEP */
#define IFX_EVADC_GLOB_TE_TFEP_LEN (8u)

/** \brief Mask for Ifx_EVADC_GLOB_TE_Bits.TFEP */
#define IFX_EVADC_GLOB_TE_TFEP_MSK (0xffu)

/** \brief Offset for Ifx_EVADC_GLOB_TE_Bits.TFEP */
#define IFX_EVADC_GLOB_TE_TFEP_OFF (0u)

/** \brief Length for Ifx_EVADC_GLOB_TE_Bits.TFES */
#define IFX_EVADC_GLOB_TE_TFES_LEN (4u)

/** \brief Mask for Ifx_EVADC_GLOB_TE_Bits.TFES */
#define IFX_EVADC_GLOB_TE_TFES_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_GLOB_TE_Bits.TFES */
#define IFX_EVADC_GLOB_TE_TFES_OFF (8u)

/** \brief Length for Ifx_EVADC_GLOB_RCR_Bits.DRCTR */
#define IFX_EVADC_GLOB_RCR_DRCTR_LEN (4u)

/** \brief Mask for Ifx_EVADC_GLOB_RCR_Bits.DRCTR */
#define IFX_EVADC_GLOB_RCR_DRCTR_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_GLOB_RCR_Bits.DRCTR */
#define IFX_EVADC_GLOB_RCR_DRCTR_OFF (16u)

/** \brief Length for Ifx_EVADC_GLOB_RCR_Bits.WFR */
#define IFX_EVADC_GLOB_RCR_WFR_LEN (1u)

/** \brief Mask for Ifx_EVADC_GLOB_RCR_Bits.WFR */
#define IFX_EVADC_GLOB_RCR_WFR_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_GLOB_RCR_Bits.WFR */
#define IFX_EVADC_GLOB_RCR_WFR_OFF (24u)

/** \brief Length for Ifx_EVADC_GLOB_RCR_Bits.SRGEN */
#define IFX_EVADC_GLOB_RCR_SRGEN_LEN (1u)

/** \brief Mask for Ifx_EVADC_GLOB_RCR_Bits.SRGEN */
#define IFX_EVADC_GLOB_RCR_SRGEN_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_GLOB_RCR_Bits.SRGEN */
#define IFX_EVADC_GLOB_RCR_SRGEN_OFF (31u)

/** \brief Length for Ifx_EVADC_GLOB_RES_Bits.RESULT */
#define IFX_EVADC_GLOB_RES_RESULT_LEN (16u)

/** \brief Mask for Ifx_EVADC_GLOB_RES_Bits.RESULT */
#define IFX_EVADC_GLOB_RES_RESULT_MSK (0xffffu)

/** \brief Offset for Ifx_EVADC_GLOB_RES_Bits.RESULT */
#define IFX_EVADC_GLOB_RES_RESULT_OFF (0u)

/** \brief Length for Ifx_EVADC_GLOB_RES_Bits.GNR */
#define IFX_EVADC_GLOB_RES_GNR_LEN (4u)

/** \brief Mask for Ifx_EVADC_GLOB_RES_Bits.GNR */
#define IFX_EVADC_GLOB_RES_GNR_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_GLOB_RES_Bits.GNR */
#define IFX_EVADC_GLOB_RES_GNR_OFF (16u)

/** \brief Length for Ifx_EVADC_GLOB_RES_Bits.CHNR */
#define IFX_EVADC_GLOB_RES_CHNR_LEN (5u)

/** \brief Mask for Ifx_EVADC_GLOB_RES_Bits.CHNR */
#define IFX_EVADC_GLOB_RES_CHNR_MSK (0x1fu)

/** \brief Offset for Ifx_EVADC_GLOB_RES_Bits.CHNR */
#define IFX_EVADC_GLOB_RES_CHNR_OFF (20u)

/** \brief Length for Ifx_EVADC_GLOB_RES_Bits.EMUX */
#define IFX_EVADC_GLOB_RES_EMUX_LEN (3u)

/** \brief Mask for Ifx_EVADC_GLOB_RES_Bits.EMUX */
#define IFX_EVADC_GLOB_RES_EMUX_MSK (0x7u)

/** \brief Offset for Ifx_EVADC_GLOB_RES_Bits.EMUX */
#define IFX_EVADC_GLOB_RES_EMUX_OFF (25u)

/** \brief Length for Ifx_EVADC_GLOB_RES_Bits.CRS */
#define IFX_EVADC_GLOB_RES_CRS_LEN (2u)

/** \brief Mask for Ifx_EVADC_GLOB_RES_Bits.CRS */
#define IFX_EVADC_GLOB_RES_CRS_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_GLOB_RES_Bits.CRS */
#define IFX_EVADC_GLOB_RES_CRS_OFF (28u)

/** \brief Length for Ifx_EVADC_GLOB_RES_Bits.VF */
#define IFX_EVADC_GLOB_RES_VF_LEN (1u)

/** \brief Mask for Ifx_EVADC_GLOB_RES_Bits.VF */
#define IFX_EVADC_GLOB_RES_VF_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_GLOB_RES_Bits.VF */
#define IFX_EVADC_GLOB_RES_VF_OFF (31u)

/** \brief Length for Ifx_EVADC_GLOB_RESD_Bits.RESULT */
#define IFX_EVADC_GLOB_RESD_RESULT_LEN (16u)

/** \brief Mask for Ifx_EVADC_GLOB_RESD_Bits.RESULT */
#define IFX_EVADC_GLOB_RESD_RESULT_MSK (0xffffu)

/** \brief Offset for Ifx_EVADC_GLOB_RESD_Bits.RESULT */
#define IFX_EVADC_GLOB_RESD_RESULT_OFF (0u)

/** \brief Length for Ifx_EVADC_GLOB_RESD_Bits.GNR */
#define IFX_EVADC_GLOB_RESD_GNR_LEN (4u)

/** \brief Mask for Ifx_EVADC_GLOB_RESD_Bits.GNR */
#define IFX_EVADC_GLOB_RESD_GNR_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_GLOB_RESD_Bits.GNR */
#define IFX_EVADC_GLOB_RESD_GNR_OFF (16u)

/** \brief Length for Ifx_EVADC_GLOB_RESD_Bits.CHNR */
#define IFX_EVADC_GLOB_RESD_CHNR_LEN (5u)

/** \brief Mask for Ifx_EVADC_GLOB_RESD_Bits.CHNR */
#define IFX_EVADC_GLOB_RESD_CHNR_MSK (0x1fu)

/** \brief Offset for Ifx_EVADC_GLOB_RESD_Bits.CHNR */
#define IFX_EVADC_GLOB_RESD_CHNR_OFF (20u)

/** \brief Length for Ifx_EVADC_GLOB_RESD_Bits.EMUX */
#define IFX_EVADC_GLOB_RESD_EMUX_LEN (3u)

/** \brief Mask for Ifx_EVADC_GLOB_RESD_Bits.EMUX */
#define IFX_EVADC_GLOB_RESD_EMUX_MSK (0x7u)

/** \brief Offset for Ifx_EVADC_GLOB_RESD_Bits.EMUX */
#define IFX_EVADC_GLOB_RESD_EMUX_OFF (25u)

/** \brief Length for Ifx_EVADC_GLOB_RESD_Bits.CRS */
#define IFX_EVADC_GLOB_RESD_CRS_LEN (2u)

/** \brief Mask for Ifx_EVADC_GLOB_RESD_Bits.CRS */
#define IFX_EVADC_GLOB_RESD_CRS_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_GLOB_RESD_Bits.CRS */
#define IFX_EVADC_GLOB_RESD_CRS_OFF (28u)

/** \brief Length for Ifx_EVADC_GLOB_RESD_Bits.VF */
#define IFX_EVADC_GLOB_RESD_VF_LEN (1u)

/** \brief Mask for Ifx_EVADC_GLOB_RESD_Bits.VF */
#define IFX_EVADC_GLOB_RESD_VF_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_GLOB_RESD_Bits.VF */
#define IFX_EVADC_GLOB_RESD_VF_OFF (31u)

/** \brief Length for Ifx_EVADC_EMUXSEL_Bits.EMUXGRP0 */
#define IFX_EVADC_EMUXSEL_EMUXGRP0_LEN (4u)

/** \brief Mask for Ifx_EVADC_EMUXSEL_Bits.EMUXGRP0 */
#define IFX_EVADC_EMUXSEL_EMUXGRP0_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_EMUXSEL_Bits.EMUXGRP0 */
#define IFX_EVADC_EMUXSEL_EMUXGRP0_OFF (0u)

/** \brief Length for Ifx_EVADC_EMUXSEL_Bits.EMUXGRP1 */
#define IFX_EVADC_EMUXSEL_EMUXGRP1_LEN (4u)

/** \brief Mask for Ifx_EVADC_EMUXSEL_Bits.EMUXGRP1 */
#define IFX_EVADC_EMUXSEL_EMUXGRP1_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_EMUXSEL_Bits.EMUXGRP1 */
#define IFX_EVADC_EMUXSEL_EMUXGRP1_OFF (4u)

/** \brief Length for Ifx_EVADC_G_TRCTR_Bits.TSC */
#define IFX_EVADC_G_TRCTR_TSC_LEN (6u)

/** \brief Mask for Ifx_EVADC_G_TRCTR_Bits.TSC */
#define IFX_EVADC_G_TRCTR_TSC_MSK (0x3fu)

/** \brief Offset for Ifx_EVADC_G_TRCTR_Bits.TSC */
#define IFX_EVADC_G_TRCTR_TSC_OFF (0u)

/** \brief Length for Ifx_EVADC_G_TRCTR_Bits.QACT */
#define IFX_EVADC_G_TRCTR_QACT_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_TRCTR_Bits.QACT */
#define IFX_EVADC_G_TRCTR_QACT_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_TRCTR_Bits.QACT */
#define IFX_EVADC_G_TRCTR_QACT_OFF (14u)

/** \brief Length for Ifx_EVADC_G_TRCTR_Bits.OV */
#define IFX_EVADC_G_TRCTR_OV_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_TRCTR_Bits.OV */
#define IFX_EVADC_G_TRCTR_OV_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_TRCTR_Bits.OV */
#define IFX_EVADC_G_TRCTR_OV_OFF (15u)

/** \brief Length for Ifx_EVADC_G_TRCTR_Bits.TSCSET */
#define IFX_EVADC_G_TRCTR_TSCSET_LEN (6u)

/** \brief Mask for Ifx_EVADC_G_TRCTR_Bits.TSCSET */
#define IFX_EVADC_G_TRCTR_TSCSET_MSK (0x3fu)

/** \brief Offset for Ifx_EVADC_G_TRCTR_Bits.TSCSET */
#define IFX_EVADC_G_TRCTR_TSCSET_OFF (16u)

/** \brief Length for Ifx_EVADC_G_TRCTR_Bits.ITSEL */
#define IFX_EVADC_G_TRCTR_ITSEL_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_TRCTR_Bits.ITSEL */
#define IFX_EVADC_G_TRCTR_ITSEL_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_TRCTR_Bits.ITSEL */
#define IFX_EVADC_G_TRCTR_ITSEL_OFF (24u)

/** \brief Length for Ifx_EVADC_G_TRCTR_Bits.SRDIS */
#define IFX_EVADC_G_TRCTR_SRDIS_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_TRCTR_Bits.SRDIS */
#define IFX_EVADC_G_TRCTR_SRDIS_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_TRCTR_Bits.SRDIS */
#define IFX_EVADC_G_TRCTR_SRDIS_OFF (28u)

/** \brief Length for Ifx_EVADC_G_TRCTR_Bits.COV */
#define IFX_EVADC_G_TRCTR_COV_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_TRCTR_Bits.COV */
#define IFX_EVADC_G_TRCTR_COV_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_TRCTR_Bits.COV */
#define IFX_EVADC_G_TRCTR_COV_OFF (31u)

/** \brief Length for Ifx_EVADC_G_ARBCFG_Bits.ANONC */
#define IFX_EVADC_G_ARBCFG_ANONC_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_ARBCFG_Bits.ANONC */
#define IFX_EVADC_G_ARBCFG_ANONC_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_ARBCFG_Bits.ANONC */
#define IFX_EVADC_G_ARBCFG_ANONC_OFF (0u)

/** \brief Length for Ifx_EVADC_G_ARBCFG_Bits.ANONS */
#define IFX_EVADC_G_ARBCFG_ANONS_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_ARBCFG_Bits.ANONS */
#define IFX_EVADC_G_ARBCFG_ANONS_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_ARBCFG_Bits.ANONS */
#define IFX_EVADC_G_ARBCFG_ANONS_OFF (16u)

/** \brief Length for Ifx_EVADC_G_ARBCFG_Bits.CSRC */
#define IFX_EVADC_G_ARBCFG_CSRC_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_ARBCFG_Bits.CSRC */
#define IFX_EVADC_G_ARBCFG_CSRC_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_ARBCFG_Bits.CSRC */
#define IFX_EVADC_G_ARBCFG_CSRC_OFF (18u)

/** \brief Length for Ifx_EVADC_G_ARBCFG_Bits.CHNR */
#define IFX_EVADC_G_ARBCFG_CHNR_LEN (5u)

/** \brief Mask for Ifx_EVADC_G_ARBCFG_Bits.CHNR */
#define IFX_EVADC_G_ARBCFG_CHNR_MSK (0x1fu)

/** \brief Offset for Ifx_EVADC_G_ARBCFG_Bits.CHNR */
#define IFX_EVADC_G_ARBCFG_CHNR_OFF (20u)

/** \brief Length for Ifx_EVADC_G_ARBCFG_Bits.SYNRUN */
#define IFX_EVADC_G_ARBCFG_SYNRUN_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_ARBCFG_Bits.SYNRUN */
#define IFX_EVADC_G_ARBCFG_SYNRUN_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_ARBCFG_Bits.SYNRUN */
#define IFX_EVADC_G_ARBCFG_SYNRUN_OFF (25u)

/** \brief Length for Ifx_EVADC_G_ARBCFG_Bits.CAL */
#define IFX_EVADC_G_ARBCFG_CAL_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_ARBCFG_Bits.CAL */
#define IFX_EVADC_G_ARBCFG_CAL_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_ARBCFG_Bits.CAL */
#define IFX_EVADC_G_ARBCFG_CAL_OFF (28u)

/** \brief Length for Ifx_EVADC_G_ARBCFG_Bits.BUSY */
#define IFX_EVADC_G_ARBCFG_BUSY_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_ARBCFG_Bits.BUSY */
#define IFX_EVADC_G_ARBCFG_BUSY_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_ARBCFG_Bits.BUSY */
#define IFX_EVADC_G_ARBCFG_BUSY_OFF (30u)

/** \brief Length for Ifx_EVADC_G_ARBCFG_Bits.SAMPLE */
#define IFX_EVADC_G_ARBCFG_SAMPLE_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_ARBCFG_Bits.SAMPLE */
#define IFX_EVADC_G_ARBCFG_SAMPLE_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_ARBCFG_Bits.SAMPLE */
#define IFX_EVADC_G_ARBCFG_SAMPLE_OFF (31u)

/** \brief Length for Ifx_EVADC_G_ARBPR_Bits.PRIO0 */
#define IFX_EVADC_G_ARBPR_PRIO0_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_ARBPR_Bits.PRIO0 */
#define IFX_EVADC_G_ARBPR_PRIO0_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_ARBPR_Bits.PRIO0 */
#define IFX_EVADC_G_ARBPR_PRIO0_OFF (0u)

/** \brief Length for Ifx_EVADC_G_ARBPR_Bits.CSM0 */
#define IFX_EVADC_G_ARBPR_CSM0_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_ARBPR_Bits.CSM0 */
#define IFX_EVADC_G_ARBPR_CSM0_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_ARBPR_Bits.CSM0 */
#define IFX_EVADC_G_ARBPR_CSM0_OFF (3u)

/** \brief Length for Ifx_EVADC_G_ARBPR_Bits.PRIO1 */
#define IFX_EVADC_G_ARBPR_PRIO1_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_ARBPR_Bits.PRIO1 */
#define IFX_EVADC_G_ARBPR_PRIO1_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_ARBPR_Bits.PRIO1 */
#define IFX_EVADC_G_ARBPR_PRIO1_OFF (4u)

/** \brief Length for Ifx_EVADC_G_ARBPR_Bits.CSM1 */
#define IFX_EVADC_G_ARBPR_CSM1_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_ARBPR_Bits.CSM1 */
#define IFX_EVADC_G_ARBPR_CSM1_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_ARBPR_Bits.CSM1 */
#define IFX_EVADC_G_ARBPR_CSM1_OFF (7u)

/** \brief Length for Ifx_EVADC_G_ARBPR_Bits.PRIO2 */
#define IFX_EVADC_G_ARBPR_PRIO2_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_ARBPR_Bits.PRIO2 */
#define IFX_EVADC_G_ARBPR_PRIO2_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_ARBPR_Bits.PRIO2 */
#define IFX_EVADC_G_ARBPR_PRIO2_OFF (8u)

/** \brief Length for Ifx_EVADC_G_ARBPR_Bits.CSM2 */
#define IFX_EVADC_G_ARBPR_CSM2_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_ARBPR_Bits.CSM2 */
#define IFX_EVADC_G_ARBPR_CSM2_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_ARBPR_Bits.CSM2 */
#define IFX_EVADC_G_ARBPR_CSM2_OFF (11u)

/** \brief Length for Ifx_EVADC_G_ARBPR_Bits.ASEN0 */
#define IFX_EVADC_G_ARBPR_ASEN0_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_ARBPR_Bits.ASEN0 */
#define IFX_EVADC_G_ARBPR_ASEN0_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_ARBPR_Bits.ASEN0 */
#define IFX_EVADC_G_ARBPR_ASEN0_OFF (24u)

/** \brief Length for Ifx_EVADC_G_ARBPR_Bits.ASEN1 */
#define IFX_EVADC_G_ARBPR_ASEN1_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_ARBPR_Bits.ASEN1 */
#define IFX_EVADC_G_ARBPR_ASEN1_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_ARBPR_Bits.ASEN1 */
#define IFX_EVADC_G_ARBPR_ASEN1_OFF (25u)

/** \brief Length for Ifx_EVADC_G_ARBPR_Bits.ASEN2 */
#define IFX_EVADC_G_ARBPR_ASEN2_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_ARBPR_Bits.ASEN2 */
#define IFX_EVADC_G_ARBPR_ASEN2_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_ARBPR_Bits.ASEN2 */
#define IFX_EVADC_G_ARBPR_ASEN2_OFF (26u)

/** \brief Length for Ifx_EVADC_G_ANCFG_Bits.IPE */
#define IFX_EVADC_G_ANCFG_IPE_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_ANCFG_Bits.IPE */
#define IFX_EVADC_G_ANCFG_IPE_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_ANCFG_Bits.IPE */
#define IFX_EVADC_G_ANCFG_IPE_OFF (0u)

/** \brief Length for Ifx_EVADC_G_ANCFG_Bits.BE */
#define IFX_EVADC_G_ANCFG_BE_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_ANCFG_Bits.BE */
#define IFX_EVADC_G_ANCFG_BE_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_ANCFG_Bits.BE */
#define IFX_EVADC_G_ANCFG_BE_OFF (1u)

/** \brief Length for Ifx_EVADC_G_ANCFG_Bits.RPE */
#define IFX_EVADC_G_ANCFG_RPE_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_ANCFG_Bits.RPE */
#define IFX_EVADC_G_ANCFG_RPE_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_ANCFG_Bits.RPE */
#define IFX_EVADC_G_ANCFG_RPE_OFF (2u)

/** \brief Length for Ifx_EVADC_G_ANCFG_Bits.RPC */
#define IFX_EVADC_G_ANCFG_RPC_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_ANCFG_Bits.RPC */
#define IFX_EVADC_G_ANCFG_RPC_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_ANCFG_Bits.RPC */
#define IFX_EVADC_G_ANCFG_RPC_OFF (3u)

/** \brief Length for Ifx_EVADC_G_ANCFG_Bits.CALSTC */
#define IFX_EVADC_G_ANCFG_CALSTC_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_ANCFG_Bits.CALSTC */
#define IFX_EVADC_G_ANCFG_CALSTC_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_ANCFG_Bits.CALSTC */
#define IFX_EVADC_G_ANCFG_CALSTC_OFF (4u)

/** \brief Length for Ifx_EVADC_G_ANCFG_Bits.DPCAL */
#define IFX_EVADC_G_ANCFG_DPCAL_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_ANCFG_Bits.DPCAL */
#define IFX_EVADC_G_ANCFG_DPCAL_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_ANCFG_Bits.DPCAL */
#define IFX_EVADC_G_ANCFG_DPCAL_OFF (6u)

/** \brief Length for Ifx_EVADC_G_ANCFG_Bits.ACSD */
#define IFX_EVADC_G_ANCFG_ACSD_LEN (3u)

/** \brief Mask for Ifx_EVADC_G_ANCFG_Bits.ACSD */
#define IFX_EVADC_G_ANCFG_ACSD_MSK (0x7u)

/** \brief Offset for Ifx_EVADC_G_ANCFG_Bits.ACSD */
#define IFX_EVADC_G_ANCFG_ACSD_OFF (16u)

/** \brief Length for Ifx_EVADC_G_ANCFG_Bits.SSE */
#define IFX_EVADC_G_ANCFG_SSE_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_ANCFG_Bits.SSE */
#define IFX_EVADC_G_ANCFG_SSE_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_ANCFG_Bits.SSE */
#define IFX_EVADC_G_ANCFG_SSE_OFF (19u)

/** \brief Length for Ifx_EVADC_G_ANCFG_Bits.DIVA */
#define IFX_EVADC_G_ANCFG_DIVA_LEN (5u)

/** \brief Mask for Ifx_EVADC_G_ANCFG_Bits.DIVA */
#define IFX_EVADC_G_ANCFG_DIVA_MSK (0x1fu)

/** \brief Offset for Ifx_EVADC_G_ANCFG_Bits.DIVA */
#define IFX_EVADC_G_ANCFG_DIVA_OFF (20u)

/** \brief Length for Ifx_EVADC_G_ANCFG_Bits.DCMSB */
#define IFX_EVADC_G_ANCFG_DCMSB_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_ANCFG_Bits.DCMSB */
#define IFX_EVADC_G_ANCFG_DCMSB_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_ANCFG_Bits.DCMSB */
#define IFX_EVADC_G_ANCFG_DCMSB_OFF (25u)

/** \brief Length for Ifx_EVADC_G_ICLASS_Bits.STCS */
#define IFX_EVADC_G_ICLASS_STCS_LEN (5u)

/** \brief Mask for Ifx_EVADC_G_ICLASS_Bits.STCS */
#define IFX_EVADC_G_ICLASS_STCS_MSK (0x1fu)

/** \brief Offset for Ifx_EVADC_G_ICLASS_Bits.STCS */
#define IFX_EVADC_G_ICLASS_STCS_OFF (0u)

/** \brief Length for Ifx_EVADC_G_ICLASS_Bits.AIPS */
#define IFX_EVADC_G_ICLASS_AIPS_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_ICLASS_Bits.AIPS */
#define IFX_EVADC_G_ICLASS_AIPS_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_ICLASS_Bits.AIPS */
#define IFX_EVADC_G_ICLASS_AIPS_OFF (6u)

/** \brief Length for Ifx_EVADC_G_ICLASS_Bits.CMS */
#define IFX_EVADC_G_ICLASS_CMS_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_ICLASS_Bits.CMS */
#define IFX_EVADC_G_ICLASS_CMS_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_ICLASS_Bits.CMS */
#define IFX_EVADC_G_ICLASS_CMS_OFF (8u)

/** \brief Length for Ifx_EVADC_G_ICLASS_Bits.SESPS */
#define IFX_EVADC_G_ICLASS_SESPS_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_ICLASS_Bits.SESPS */
#define IFX_EVADC_G_ICLASS_SESPS_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_ICLASS_Bits.SESPS */
#define IFX_EVADC_G_ICLASS_SESPS_OFF (10u)

/** \brief Length for Ifx_EVADC_G_ICLASS_Bits.STCE */
#define IFX_EVADC_G_ICLASS_STCE_LEN (5u)

/** \brief Mask for Ifx_EVADC_G_ICLASS_Bits.STCE */
#define IFX_EVADC_G_ICLASS_STCE_MSK (0x1fu)

/** \brief Offset for Ifx_EVADC_G_ICLASS_Bits.STCE */
#define IFX_EVADC_G_ICLASS_STCE_OFF (16u)

/** \brief Length for Ifx_EVADC_G_ICLASS_Bits.AIPE */
#define IFX_EVADC_G_ICLASS_AIPE_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_ICLASS_Bits.AIPE */
#define IFX_EVADC_G_ICLASS_AIPE_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_ICLASS_Bits.AIPE */
#define IFX_EVADC_G_ICLASS_AIPE_OFF (22u)

/** \brief Length for Ifx_EVADC_G_ICLASS_Bits.CME */
#define IFX_EVADC_G_ICLASS_CME_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_ICLASS_Bits.CME */
#define IFX_EVADC_G_ICLASS_CME_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_ICLASS_Bits.CME */
#define IFX_EVADC_G_ICLASS_CME_OFF (24u)

/** \brief Length for Ifx_EVADC_G_ICLASS_Bits.SESPE */
#define IFX_EVADC_G_ICLASS_SESPE_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_ICLASS_Bits.SESPE */
#define IFX_EVADC_G_ICLASS_SESPE_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_ICLASS_Bits.SESPE */
#define IFX_EVADC_G_ICLASS_SESPE_OFF (26u)

/** \brief Length for Ifx_EVADC_G_ALIAS_Bits.ALIAS0 */
#define IFX_EVADC_G_ALIAS_ALIAS0_LEN (5u)

/** \brief Mask for Ifx_EVADC_G_ALIAS_Bits.ALIAS0 */
#define IFX_EVADC_G_ALIAS_ALIAS0_MSK (0x1fu)

/** \brief Offset for Ifx_EVADC_G_ALIAS_Bits.ALIAS0 */
#define IFX_EVADC_G_ALIAS_ALIAS0_OFF (0u)

/** \brief Length for Ifx_EVADC_G_ALIAS_Bits.ALIAS1 */
#define IFX_EVADC_G_ALIAS_ALIAS1_LEN (5u)

/** \brief Mask for Ifx_EVADC_G_ALIAS_Bits.ALIAS1 */
#define IFX_EVADC_G_ALIAS_ALIAS1_MSK (0x1fu)

/** \brief Offset for Ifx_EVADC_G_ALIAS_Bits.ALIAS1 */
#define IFX_EVADC_G_ALIAS_ALIAS1_OFF (8u)

/** \brief Length for Ifx_EVADC_G_BOUND_Bits.BOUNDARY0 */
#define IFX_EVADC_G_BOUND_BOUNDARY0_LEN (12u)

/** \brief Mask for Ifx_EVADC_G_BOUND_Bits.BOUNDARY0 */
#define IFX_EVADC_G_BOUND_BOUNDARY0_MSK (0xfffu)

/** \brief Offset for Ifx_EVADC_G_BOUND_Bits.BOUNDARY0 */
#define IFX_EVADC_G_BOUND_BOUNDARY0_OFF (0u)

/** \brief Length for Ifx_EVADC_G_BOUND_Bits.BOUNDARY1 */
#define IFX_EVADC_G_BOUND_BOUNDARY1_LEN (12u)

/** \brief Mask for Ifx_EVADC_G_BOUND_Bits.BOUNDARY1 */
#define IFX_EVADC_G_BOUND_BOUNDARY1_MSK (0xfffu)

/** \brief Offset for Ifx_EVADC_G_BOUND_Bits.BOUNDARY1 */
#define IFX_EVADC_G_BOUND_BOUNDARY1_OFF (16u)

/** \brief Length for Ifx_EVADC_G_SYNCTR_Bits.STSEL */
#define IFX_EVADC_G_SYNCTR_STSEL_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_SYNCTR_Bits.STSEL */
#define IFX_EVADC_G_SYNCTR_STSEL_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_SYNCTR_Bits.STSEL */
#define IFX_EVADC_G_SYNCTR_STSEL_OFF (0u)

/** \brief Length for Ifx_EVADC_G_SYNCTR_Bits.EVALR1 */
#define IFX_EVADC_G_SYNCTR_EVALR1_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_SYNCTR_Bits.EVALR1 */
#define IFX_EVADC_G_SYNCTR_EVALR1_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_SYNCTR_Bits.EVALR1 */
#define IFX_EVADC_G_SYNCTR_EVALR1_OFF (4u)

/** \brief Length for Ifx_EVADC_G_SYNCTR_Bits.EVALR2 */
#define IFX_EVADC_G_SYNCTR_EVALR2_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_SYNCTR_Bits.EVALR2 */
#define IFX_EVADC_G_SYNCTR_EVALR2_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_SYNCTR_Bits.EVALR2 */
#define IFX_EVADC_G_SYNCTR_EVALR2_OFF (5u)

/** \brief Length for Ifx_EVADC_G_SYNCTR_Bits.EVALR3 */
#define IFX_EVADC_G_SYNCTR_EVALR3_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_SYNCTR_Bits.EVALR3 */
#define IFX_EVADC_G_SYNCTR_EVALR3_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_SYNCTR_Bits.EVALR3 */
#define IFX_EVADC_G_SYNCTR_EVALR3_OFF (6u)

/** \brief Length for Ifx_EVADC_G_Q_QCTRL_Bits.SRCRESREG */
#define IFX_EVADC_G_Q_QCTRL_SRCRESREG_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_Q_QCTRL_Bits.SRCRESREG */
#define IFX_EVADC_G_Q_QCTRL_SRCRESREG_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_Q_QCTRL_Bits.SRCRESREG */
#define IFX_EVADC_G_Q_QCTRL_SRCRESREG_OFF (0u)

/** \brief Length for Ifx_EVADC_G_Q_QCTRL_Bits.TRSEL */
#define IFX_EVADC_G_Q_QCTRL_TRSEL_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_Q_QCTRL_Bits.TRSEL */
#define IFX_EVADC_G_Q_QCTRL_TRSEL_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_Q_QCTRL_Bits.TRSEL */
#define IFX_EVADC_G_Q_QCTRL_TRSEL_OFF (6u)

/** \brief Length for Ifx_EVADC_G_Q_QCTRL_Bits.XTSEL */
#define IFX_EVADC_G_Q_QCTRL_XTSEL_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_Q_QCTRL_Bits.XTSEL */
#define IFX_EVADC_G_Q_QCTRL_XTSEL_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_Q_QCTRL_Bits.XTSEL */
#define IFX_EVADC_G_Q_QCTRL_XTSEL_OFF (8u)

/** \brief Length for Ifx_EVADC_G_Q_QCTRL_Bits.XTLVL */
#define IFX_EVADC_G_Q_QCTRL_XTLVL_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QCTRL_Bits.XTLVL */
#define IFX_EVADC_G_Q_QCTRL_XTLVL_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QCTRL_Bits.XTLVL */
#define IFX_EVADC_G_Q_QCTRL_XTLVL_OFF (12u)

/** \brief Length for Ifx_EVADC_G_Q_QCTRL_Bits.XTMODE */
#define IFX_EVADC_G_Q_QCTRL_XTMODE_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_Q_QCTRL_Bits.XTMODE */
#define IFX_EVADC_G_Q_QCTRL_XTMODE_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_Q_QCTRL_Bits.XTMODE */
#define IFX_EVADC_G_Q_QCTRL_XTMODE_OFF (13u)

/** \brief Length for Ifx_EVADC_G_Q_QCTRL_Bits.XTWC */
#define IFX_EVADC_G_Q_QCTRL_XTWC_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QCTRL_Bits.XTWC */
#define IFX_EVADC_G_Q_QCTRL_XTWC_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QCTRL_Bits.XTWC */
#define IFX_EVADC_G_Q_QCTRL_XTWC_OFF (15u)

/** \brief Length for Ifx_EVADC_G_Q_QCTRL_Bits.GTSEL */
#define IFX_EVADC_G_Q_QCTRL_GTSEL_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_Q_QCTRL_Bits.GTSEL */
#define IFX_EVADC_G_Q_QCTRL_GTSEL_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_Q_QCTRL_Bits.GTSEL */
#define IFX_EVADC_G_Q_QCTRL_GTSEL_OFF (16u)

/** \brief Length for Ifx_EVADC_G_Q_QCTRL_Bits.GTLVL */
#define IFX_EVADC_G_Q_QCTRL_GTLVL_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QCTRL_Bits.GTLVL */
#define IFX_EVADC_G_Q_QCTRL_GTLVL_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QCTRL_Bits.GTLVL */
#define IFX_EVADC_G_Q_QCTRL_GTLVL_OFF (20u)

/** \brief Length for Ifx_EVADC_G_Q_QCTRL_Bits.GTWC */
#define IFX_EVADC_G_Q_QCTRL_GTWC_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QCTRL_Bits.GTWC */
#define IFX_EVADC_G_Q_QCTRL_GTWC_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QCTRL_Bits.GTWC */
#define IFX_EVADC_G_Q_QCTRL_GTWC_OFF (23u)

/** \brief Length for Ifx_EVADC_G_Q_QCTRL_Bits.TMEN */
#define IFX_EVADC_G_Q_QCTRL_TMEN_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QCTRL_Bits.TMEN */
#define IFX_EVADC_G_Q_QCTRL_TMEN_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QCTRL_Bits.TMEN */
#define IFX_EVADC_G_Q_QCTRL_TMEN_OFF (28u)

/** \brief Length for Ifx_EVADC_G_Q_QCTRL_Bits.TMWC */
#define IFX_EVADC_G_Q_QCTRL_TMWC_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QCTRL_Bits.TMWC */
#define IFX_EVADC_G_Q_QCTRL_TMWC_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QCTRL_Bits.TMWC */
#define IFX_EVADC_G_Q_QCTRL_TMWC_OFF (31u)

/** \brief Length for Ifx_EVADC_G_Q_QMR_Bits.ENGT */
#define IFX_EVADC_G_Q_QMR_ENGT_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_Q_QMR_Bits.ENGT */
#define IFX_EVADC_G_Q_QMR_ENGT_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_Q_QMR_Bits.ENGT */
#define IFX_EVADC_G_Q_QMR_ENGT_OFF (0u)

/** \brief Length for Ifx_EVADC_G_Q_QMR_Bits.ENTR */
#define IFX_EVADC_G_Q_QMR_ENTR_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QMR_Bits.ENTR */
#define IFX_EVADC_G_Q_QMR_ENTR_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QMR_Bits.ENTR */
#define IFX_EVADC_G_Q_QMR_ENTR_OFF (2u)

/** \brief Length for Ifx_EVADC_G_Q_QMR_Bits.CLRV */
#define IFX_EVADC_G_Q_QMR_CLRV_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QMR_Bits.CLRV */
#define IFX_EVADC_G_Q_QMR_CLRV_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QMR_Bits.CLRV */
#define IFX_EVADC_G_Q_QMR_CLRV_OFF (8u)

/** \brief Length for Ifx_EVADC_G_Q_QMR_Bits.TREV */
#define IFX_EVADC_G_Q_QMR_TREV_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QMR_Bits.TREV */
#define IFX_EVADC_G_Q_QMR_TREV_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QMR_Bits.TREV */
#define IFX_EVADC_G_Q_QMR_TREV_OFF (9u)

/** \brief Length for Ifx_EVADC_G_Q_QMR_Bits.FLUSH */
#define IFX_EVADC_G_Q_QMR_FLUSH_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QMR_Bits.FLUSH */
#define IFX_EVADC_G_Q_QMR_FLUSH_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QMR_Bits.FLUSH */
#define IFX_EVADC_G_Q_QMR_FLUSH_OFF (10u)

/** \brief Length for Ifx_EVADC_G_Q_QMR_Bits.CEV */
#define IFX_EVADC_G_Q_QMR_CEV_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QMR_Bits.CEV */
#define IFX_EVADC_G_Q_QMR_CEV_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QMR_Bits.CEV */
#define IFX_EVADC_G_Q_QMR_CEV_OFF (11u)

/** \brief Length for Ifx_EVADC_G_Q_QMR_Bits.RPTDIS */
#define IFX_EVADC_G_Q_QMR_RPTDIS_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QMR_Bits.RPTDIS */
#define IFX_EVADC_G_Q_QMR_RPTDIS_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QMR_Bits.RPTDIS */
#define IFX_EVADC_G_Q_QMR_RPTDIS_OFF (16u)

/** \brief Length for Ifx_EVADC_G_Q_QSR_Bits.FILL */
#define IFX_EVADC_G_Q_QSR_FILL_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_Q_QSR_Bits.FILL */
#define IFX_EVADC_G_Q_QSR_FILL_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_Q_QSR_Bits.FILL */
#define IFX_EVADC_G_Q_QSR_FILL_OFF (0u)

/** \brief Length for Ifx_EVADC_G_Q_QSR_Bits.EMPTY */
#define IFX_EVADC_G_Q_QSR_EMPTY_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QSR_Bits.EMPTY */
#define IFX_EVADC_G_Q_QSR_EMPTY_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QSR_Bits.EMPTY */
#define IFX_EVADC_G_Q_QSR_EMPTY_OFF (5u)

/** \brief Length for Ifx_EVADC_G_Q_QSR_Bits.REQGT */
#define IFX_EVADC_G_Q_QSR_REQGT_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QSR_Bits.REQGT */
#define IFX_EVADC_G_Q_QSR_REQGT_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QSR_Bits.REQGT */
#define IFX_EVADC_G_Q_QSR_REQGT_OFF (7u)

/** \brief Length for Ifx_EVADC_G_Q_QSR_Bits.EV */
#define IFX_EVADC_G_Q_QSR_EV_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QSR_Bits.EV */
#define IFX_EVADC_G_Q_QSR_EV_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QSR_Bits.EV */
#define IFX_EVADC_G_Q_QSR_EV_OFF (8u)

/** \brief Length for Ifx_EVADC_G_Q_Q0R_Bits.REQCHNR */
#define IFX_EVADC_G_Q_Q0R_REQCHNR_LEN (5u)

/** \brief Mask for Ifx_EVADC_G_Q_Q0R_Bits.REQCHNR */
#define IFX_EVADC_G_Q_Q0R_REQCHNR_MSK (0x1fu)

/** \brief Offset for Ifx_EVADC_G_Q_Q0R_Bits.REQCHNR */
#define IFX_EVADC_G_Q_Q0R_REQCHNR_OFF (0u)

/** \brief Length for Ifx_EVADC_G_Q_Q0R_Bits.RF */
#define IFX_EVADC_G_Q_Q0R_RF_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_Q0R_Bits.RF */
#define IFX_EVADC_G_Q_Q0R_RF_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_Q0R_Bits.RF */
#define IFX_EVADC_G_Q_Q0R_RF_OFF (5u)

/** \brief Length for Ifx_EVADC_G_Q_Q0R_Bits.ENSI */
#define IFX_EVADC_G_Q_Q0R_ENSI_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_Q0R_Bits.ENSI */
#define IFX_EVADC_G_Q_Q0R_ENSI_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_Q0R_Bits.ENSI */
#define IFX_EVADC_G_Q_Q0R_ENSI_OFF (6u)

/** \brief Length for Ifx_EVADC_G_Q_Q0R_Bits.EXTR */
#define IFX_EVADC_G_Q_Q0R_EXTR_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_Q0R_Bits.EXTR */
#define IFX_EVADC_G_Q_Q0R_EXTR_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_Q0R_Bits.EXTR */
#define IFX_EVADC_G_Q_Q0R_EXTR_OFF (7u)

/** \brief Length for Ifx_EVADC_G_Q_Q0R_Bits.V */
#define IFX_EVADC_G_Q_Q0R_V_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_Q0R_Bits.V */
#define IFX_EVADC_G_Q_Q0R_V_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_Q0R_Bits.V */
#define IFX_EVADC_G_Q_Q0R_V_OFF (8u)

/** \brief Length for Ifx_EVADC_G_Q_Q0R_Bits.PDD */
#define IFX_EVADC_G_Q_Q0R_PDD_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_Q0R_Bits.PDD */
#define IFX_EVADC_G_Q_Q0R_PDD_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_Q0R_Bits.PDD */
#define IFX_EVADC_G_Q_Q0R_PDD_OFF (9u)

/** \brief Length for Ifx_EVADC_G_Q_Q0R_Bits.MDPD */
#define IFX_EVADC_G_Q_Q0R_MDPD_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_Q0R_Bits.MDPD */
#define IFX_EVADC_G_Q_Q0R_MDPD_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_Q0R_Bits.MDPD */
#define IFX_EVADC_G_Q_Q0R_MDPD_OFF (10u)

/** \brief Length for Ifx_EVADC_G_Q_Q0R_Bits.MDPU */
#define IFX_EVADC_G_Q_Q0R_MDPU_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_Q0R_Bits.MDPU */
#define IFX_EVADC_G_Q_Q0R_MDPU_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_Q0R_Bits.MDPU */
#define IFX_EVADC_G_Q_Q0R_MDPU_OFF (11u)

/** \brief Length for Ifx_EVADC_G_Q_Q0R_Bits.CDEN */
#define IFX_EVADC_G_Q_Q0R_CDEN_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_Q0R_Bits.CDEN */
#define IFX_EVADC_G_Q_Q0R_CDEN_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_Q0R_Bits.CDEN */
#define IFX_EVADC_G_Q_Q0R_CDEN_OFF (12u)

/** \brief Length for Ifx_EVADC_G_Q_Q0R_Bits.CDSEL */
#define IFX_EVADC_G_Q_Q0R_CDSEL_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_Q_Q0R_Bits.CDSEL */
#define IFX_EVADC_G_Q_Q0R_CDSEL_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_Q_Q0R_Bits.CDSEL */
#define IFX_EVADC_G_Q_Q0R_CDSEL_OFF (13u)

/** \brief Length for Ifx_EVADC_G_Q_QINR_Bits.REQCHNR */
#define IFX_EVADC_G_Q_QINR_REQCHNR_LEN (5u)

/** \brief Mask for Ifx_EVADC_G_Q_QINR_Bits.REQCHNR */
#define IFX_EVADC_G_Q_QINR_REQCHNR_MSK (0x1fu)

/** \brief Offset for Ifx_EVADC_G_Q_QINR_Bits.REQCHNR */
#define IFX_EVADC_G_Q_QINR_REQCHNR_OFF (0u)

/** \brief Length for Ifx_EVADC_G_Q_QINR_Bits.RF */
#define IFX_EVADC_G_Q_QINR_RF_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QINR_Bits.RF */
#define IFX_EVADC_G_Q_QINR_RF_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QINR_Bits.RF */
#define IFX_EVADC_G_Q_QINR_RF_OFF (5u)

/** \brief Length for Ifx_EVADC_G_Q_QINR_Bits.ENSI */
#define IFX_EVADC_G_Q_QINR_ENSI_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QINR_Bits.ENSI */
#define IFX_EVADC_G_Q_QINR_ENSI_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QINR_Bits.ENSI */
#define IFX_EVADC_G_Q_QINR_ENSI_OFF (6u)

/** \brief Length for Ifx_EVADC_G_Q_QINR_Bits.EXTR */
#define IFX_EVADC_G_Q_QINR_EXTR_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QINR_Bits.EXTR */
#define IFX_EVADC_G_Q_QINR_EXTR_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QINR_Bits.EXTR */
#define IFX_EVADC_G_Q_QINR_EXTR_OFF (7u)

/** \brief Length for Ifx_EVADC_G_Q_QINR_Bits.PDD */
#define IFX_EVADC_G_Q_QINR_PDD_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QINR_Bits.PDD */
#define IFX_EVADC_G_Q_QINR_PDD_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QINR_Bits.PDD */
#define IFX_EVADC_G_Q_QINR_PDD_OFF (9u)

/** \brief Length for Ifx_EVADC_G_Q_QINR_Bits.MDPD */
#define IFX_EVADC_G_Q_QINR_MDPD_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QINR_Bits.MDPD */
#define IFX_EVADC_G_Q_QINR_MDPD_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QINR_Bits.MDPD */
#define IFX_EVADC_G_Q_QINR_MDPD_OFF (10u)

/** \brief Length for Ifx_EVADC_G_Q_QINR_Bits.MDPU */
#define IFX_EVADC_G_Q_QINR_MDPU_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QINR_Bits.MDPU */
#define IFX_EVADC_G_Q_QINR_MDPU_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QINR_Bits.MDPU */
#define IFX_EVADC_G_Q_QINR_MDPU_OFF (11u)

/** \brief Length for Ifx_EVADC_G_Q_QINR_Bits.CDEN */
#define IFX_EVADC_G_Q_QINR_CDEN_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QINR_Bits.CDEN */
#define IFX_EVADC_G_Q_QINR_CDEN_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QINR_Bits.CDEN */
#define IFX_EVADC_G_Q_QINR_CDEN_OFF (12u)

/** \brief Length for Ifx_EVADC_G_Q_QINR_Bits.CDSEL */
#define IFX_EVADC_G_Q_QINR_CDSEL_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_Q_QINR_Bits.CDSEL */
#define IFX_EVADC_G_Q_QINR_CDSEL_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_Q_QINR_Bits.CDSEL */
#define IFX_EVADC_G_Q_QINR_CDSEL_OFF (13u)

/** \brief Length for Ifx_EVADC_G_Q_QBUR_Bits.REQCHNR */
#define IFX_EVADC_G_Q_QBUR_REQCHNR_LEN (5u)

/** \brief Mask for Ifx_EVADC_G_Q_QBUR_Bits.REQCHNR */
#define IFX_EVADC_G_Q_QBUR_REQCHNR_MSK (0x1fu)

/** \brief Offset for Ifx_EVADC_G_Q_QBUR_Bits.REQCHNR */
#define IFX_EVADC_G_Q_QBUR_REQCHNR_OFF (0u)

/** \brief Length for Ifx_EVADC_G_Q_QBUR_Bits.RF */
#define IFX_EVADC_G_Q_QBUR_RF_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QBUR_Bits.RF */
#define IFX_EVADC_G_Q_QBUR_RF_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QBUR_Bits.RF */
#define IFX_EVADC_G_Q_QBUR_RF_OFF (5u)

/** \brief Length for Ifx_EVADC_G_Q_QBUR_Bits.ENSI */
#define IFX_EVADC_G_Q_QBUR_ENSI_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QBUR_Bits.ENSI */
#define IFX_EVADC_G_Q_QBUR_ENSI_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QBUR_Bits.ENSI */
#define IFX_EVADC_G_Q_QBUR_ENSI_OFF (6u)

/** \brief Length for Ifx_EVADC_G_Q_QBUR_Bits.EXTR */
#define IFX_EVADC_G_Q_QBUR_EXTR_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QBUR_Bits.EXTR */
#define IFX_EVADC_G_Q_QBUR_EXTR_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QBUR_Bits.EXTR */
#define IFX_EVADC_G_Q_QBUR_EXTR_OFF (7u)

/** \brief Length for Ifx_EVADC_G_Q_QBUR_Bits.V */
#define IFX_EVADC_G_Q_QBUR_V_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QBUR_Bits.V */
#define IFX_EVADC_G_Q_QBUR_V_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QBUR_Bits.V */
#define IFX_EVADC_G_Q_QBUR_V_OFF (8u)

/** \brief Length for Ifx_EVADC_G_Q_QBUR_Bits.PDD */
#define IFX_EVADC_G_Q_QBUR_PDD_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QBUR_Bits.PDD */
#define IFX_EVADC_G_Q_QBUR_PDD_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QBUR_Bits.PDD */
#define IFX_EVADC_G_Q_QBUR_PDD_OFF (9u)

/** \brief Length for Ifx_EVADC_G_Q_QBUR_Bits.MDPD */
#define IFX_EVADC_G_Q_QBUR_MDPD_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QBUR_Bits.MDPD */
#define IFX_EVADC_G_Q_QBUR_MDPD_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QBUR_Bits.MDPD */
#define IFX_EVADC_G_Q_QBUR_MDPD_OFF (10u)

/** \brief Length for Ifx_EVADC_G_Q_QBUR_Bits.MDPU */
#define IFX_EVADC_G_Q_QBUR_MDPU_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QBUR_Bits.MDPU */
#define IFX_EVADC_G_Q_QBUR_MDPU_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QBUR_Bits.MDPU */
#define IFX_EVADC_G_Q_QBUR_MDPU_OFF (11u)

/** \brief Length for Ifx_EVADC_G_Q_QBUR_Bits.CDEN */
#define IFX_EVADC_G_Q_QBUR_CDEN_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_QBUR_Bits.CDEN */
#define IFX_EVADC_G_Q_QBUR_CDEN_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_QBUR_Bits.CDEN */
#define IFX_EVADC_G_Q_QBUR_CDEN_OFF (12u)

/** \brief Length for Ifx_EVADC_G_Q_QBUR_Bits.CDSEL */
#define IFX_EVADC_G_Q_QBUR_CDSEL_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_Q_QBUR_Bits.CDSEL */
#define IFX_EVADC_G_Q_QBUR_CDSEL_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_Q_QBUR_Bits.CDSEL */
#define IFX_EVADC_G_Q_QBUR_CDSEL_OFF (13u)

/** \brief Length for Ifx_EVADC_G_Q_REQTM_Bits.SEQMOD */
#define IFX_EVADC_G_Q_REQTM_SEQMOD_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_Q_REQTM_Bits.SEQMOD */
#define IFX_EVADC_G_Q_REQTM_SEQMOD_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_Q_REQTM_Bits.SEQMOD */
#define IFX_EVADC_G_Q_REQTM_SEQMOD_OFF (0u)

/** \brief Length for Ifx_EVADC_G_Q_REQTM_Bits.SEQTIMSET */
#define IFX_EVADC_G_Q_REQTM_SEQTIMSET_LEN (10u)

/** \brief Mask for Ifx_EVADC_G_Q_REQTM_Bits.SEQTIMSET */
#define IFX_EVADC_G_Q_REQTM_SEQTIMSET_MSK (0x3ffu)

/** \brief Offset for Ifx_EVADC_G_Q_REQTM_Bits.SEQTIMSET */
#define IFX_EVADC_G_Q_REQTM_SEQTIMSET_OFF (6u)

/** \brief Length for Ifx_EVADC_G_Q_REQTM_Bits.REQTS */
#define IFX_EVADC_G_Q_REQTM_REQTS_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_REQTM_Bits.REQTS */
#define IFX_EVADC_G_Q_REQTM_REQTS_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_REQTM_Bits.REQTS */
#define IFX_EVADC_G_Q_REQTM_REQTS_OFF (16u)

/** \brief Length for Ifx_EVADC_G_Q_REQTM_Bits.ENTR */
#define IFX_EVADC_G_Q_REQTM_ENTR_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_Q_REQTM_Bits.ENTR */
#define IFX_EVADC_G_Q_REQTM_ENTR_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_Q_REQTM_Bits.ENTR */
#define IFX_EVADC_G_Q_REQTM_ENTR_OFF (17u)

/** \brief Length for Ifx_EVADC_G_Q_REQTM_Bits.SEQTIMOFF */
#define IFX_EVADC_G_Q_REQTM_SEQTIMOFF_LEN (10u)

/** \brief Mask for Ifx_EVADC_G_Q_REQTM_Bits.SEQTIMOFF */
#define IFX_EVADC_G_Q_REQTM_SEQTIMOFF_MSK (0x3ffu)

/** \brief Offset for Ifx_EVADC_G_Q_REQTM_Bits.SEQTIMOFF */
#define IFX_EVADC_G_Q_REQTM_SEQTIMOFF_OFF (22u)

/** \brief Length for Ifx_EVADC_G_Q_REQTS_Bits.SEQTIMER */
#define IFX_EVADC_G_Q_REQTS_SEQTIMER_LEN (10u)

/** \brief Mask for Ifx_EVADC_G_Q_REQTS_Bits.SEQTIMER */
#define IFX_EVADC_G_Q_REQTS_SEQTIMER_MSK (0x3ffu)

/** \brief Offset for Ifx_EVADC_G_Q_REQTS_Bits.SEQTIMER */
#define IFX_EVADC_G_Q_REQTS_SEQTIMER_OFF (6u)

/** \brief Length for Ifx_EVADC_G_CEFLAG_Bits.CEV0 */
#define IFX_EVADC_G_CEFLAG_CEV0_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFLAG_Bits.CEV0 */
#define IFX_EVADC_G_CEFLAG_CEV0_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFLAG_Bits.CEV0 */
#define IFX_EVADC_G_CEFLAG_CEV0_OFF (0u)

/** \brief Length for Ifx_EVADC_G_CEFLAG_Bits.CEV1 */
#define IFX_EVADC_G_CEFLAG_CEV1_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFLAG_Bits.CEV1 */
#define IFX_EVADC_G_CEFLAG_CEV1_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFLAG_Bits.CEV1 */
#define IFX_EVADC_G_CEFLAG_CEV1_OFF (1u)

/** \brief Length for Ifx_EVADC_G_CEFLAG_Bits.CEV2 */
#define IFX_EVADC_G_CEFLAG_CEV2_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFLAG_Bits.CEV2 */
#define IFX_EVADC_G_CEFLAG_CEV2_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFLAG_Bits.CEV2 */
#define IFX_EVADC_G_CEFLAG_CEV2_OFF (2u)

/** \brief Length for Ifx_EVADC_G_CEFLAG_Bits.CEV3 */
#define IFX_EVADC_G_CEFLAG_CEV3_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFLAG_Bits.CEV3 */
#define IFX_EVADC_G_CEFLAG_CEV3_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFLAG_Bits.CEV3 */
#define IFX_EVADC_G_CEFLAG_CEV3_OFF (3u)

/** \brief Length for Ifx_EVADC_G_CEFLAG_Bits.CEV4 */
#define IFX_EVADC_G_CEFLAG_CEV4_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFLAG_Bits.CEV4 */
#define IFX_EVADC_G_CEFLAG_CEV4_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFLAG_Bits.CEV4 */
#define IFX_EVADC_G_CEFLAG_CEV4_OFF (4u)

/** \brief Length for Ifx_EVADC_G_CEFLAG_Bits.CEV5 */
#define IFX_EVADC_G_CEFLAG_CEV5_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFLAG_Bits.CEV5 */
#define IFX_EVADC_G_CEFLAG_CEV5_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFLAG_Bits.CEV5 */
#define IFX_EVADC_G_CEFLAG_CEV5_OFF (5u)

/** \brief Length for Ifx_EVADC_G_CEFLAG_Bits.CEV6 */
#define IFX_EVADC_G_CEFLAG_CEV6_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFLAG_Bits.CEV6 */
#define IFX_EVADC_G_CEFLAG_CEV6_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFLAG_Bits.CEV6 */
#define IFX_EVADC_G_CEFLAG_CEV6_OFF (6u)

/** \brief Length for Ifx_EVADC_G_CEFLAG_Bits.CEV7 */
#define IFX_EVADC_G_CEFLAG_CEV7_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFLAG_Bits.CEV7 */
#define IFX_EVADC_G_CEFLAG_CEV7_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFLAG_Bits.CEV7 */
#define IFX_EVADC_G_CEFLAG_CEV7_OFF (7u)

/** \brief Length for Ifx_EVADC_G_CEFLAG_Bits.CEV8 */
#define IFX_EVADC_G_CEFLAG_CEV8_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFLAG_Bits.CEV8 */
#define IFX_EVADC_G_CEFLAG_CEV8_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFLAG_Bits.CEV8 */
#define IFX_EVADC_G_CEFLAG_CEV8_OFF (8u)

/** \brief Length for Ifx_EVADC_G_CEFLAG_Bits.CEV9 */
#define IFX_EVADC_G_CEFLAG_CEV9_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFLAG_Bits.CEV9 */
#define IFX_EVADC_G_CEFLAG_CEV9_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFLAG_Bits.CEV9 */
#define IFX_EVADC_G_CEFLAG_CEV9_OFF (9u)

/** \brief Length for Ifx_EVADC_G_CEFLAG_Bits.CEV10 */
#define IFX_EVADC_G_CEFLAG_CEV10_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFLAG_Bits.CEV10 */
#define IFX_EVADC_G_CEFLAG_CEV10_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFLAG_Bits.CEV10 */
#define IFX_EVADC_G_CEFLAG_CEV10_OFF (10u)

/** \brief Length for Ifx_EVADC_G_CEFLAG_Bits.CEV11 */
#define IFX_EVADC_G_CEFLAG_CEV11_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFLAG_Bits.CEV11 */
#define IFX_EVADC_G_CEFLAG_CEV11_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFLAG_Bits.CEV11 */
#define IFX_EVADC_G_CEFLAG_CEV11_OFF (11u)

/** \brief Length for Ifx_EVADC_G_CEFLAG_Bits.CEV12 */
#define IFX_EVADC_G_CEFLAG_CEV12_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFLAG_Bits.CEV12 */
#define IFX_EVADC_G_CEFLAG_CEV12_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFLAG_Bits.CEV12 */
#define IFX_EVADC_G_CEFLAG_CEV12_OFF (12u)

/** \brief Length for Ifx_EVADC_G_CEFLAG_Bits.CEV13 */
#define IFX_EVADC_G_CEFLAG_CEV13_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFLAG_Bits.CEV13 */
#define IFX_EVADC_G_CEFLAG_CEV13_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFLAG_Bits.CEV13 */
#define IFX_EVADC_G_CEFLAG_CEV13_OFF (13u)

/** \brief Length for Ifx_EVADC_G_CEFLAG_Bits.CEV14 */
#define IFX_EVADC_G_CEFLAG_CEV14_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFLAG_Bits.CEV14 */
#define IFX_EVADC_G_CEFLAG_CEV14_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFLAG_Bits.CEV14 */
#define IFX_EVADC_G_CEFLAG_CEV14_OFF (14u)

/** \brief Length for Ifx_EVADC_G_CEFLAG_Bits.CEV15 */
#define IFX_EVADC_G_CEFLAG_CEV15_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFLAG_Bits.CEV15 */
#define IFX_EVADC_G_CEFLAG_CEV15_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFLAG_Bits.CEV15 */
#define IFX_EVADC_G_CEFLAG_CEV15_OFF (15u)

/** \brief Length for Ifx_EVADC_G_REFLAG_Bits.REV0 */
#define IFX_EVADC_G_REFLAG_REV0_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFLAG_Bits.REV0 */
#define IFX_EVADC_G_REFLAG_REV0_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFLAG_Bits.REV0 */
#define IFX_EVADC_G_REFLAG_REV0_OFF (0u)

/** \brief Length for Ifx_EVADC_G_REFLAG_Bits.REV1 */
#define IFX_EVADC_G_REFLAG_REV1_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFLAG_Bits.REV1 */
#define IFX_EVADC_G_REFLAG_REV1_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFLAG_Bits.REV1 */
#define IFX_EVADC_G_REFLAG_REV1_OFF (1u)

/** \brief Length for Ifx_EVADC_G_REFLAG_Bits.REV2 */
#define IFX_EVADC_G_REFLAG_REV2_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFLAG_Bits.REV2 */
#define IFX_EVADC_G_REFLAG_REV2_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFLAG_Bits.REV2 */
#define IFX_EVADC_G_REFLAG_REV2_OFF (2u)

/** \brief Length for Ifx_EVADC_G_REFLAG_Bits.REV3 */
#define IFX_EVADC_G_REFLAG_REV3_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFLAG_Bits.REV3 */
#define IFX_EVADC_G_REFLAG_REV3_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFLAG_Bits.REV3 */
#define IFX_EVADC_G_REFLAG_REV3_OFF (3u)

/** \brief Length for Ifx_EVADC_G_REFLAG_Bits.REV4 */
#define IFX_EVADC_G_REFLAG_REV4_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFLAG_Bits.REV4 */
#define IFX_EVADC_G_REFLAG_REV4_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFLAG_Bits.REV4 */
#define IFX_EVADC_G_REFLAG_REV4_OFF (4u)

/** \brief Length for Ifx_EVADC_G_REFLAG_Bits.REV5 */
#define IFX_EVADC_G_REFLAG_REV5_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFLAG_Bits.REV5 */
#define IFX_EVADC_G_REFLAG_REV5_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFLAG_Bits.REV5 */
#define IFX_EVADC_G_REFLAG_REV5_OFF (5u)

/** \brief Length for Ifx_EVADC_G_REFLAG_Bits.REV6 */
#define IFX_EVADC_G_REFLAG_REV6_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFLAG_Bits.REV6 */
#define IFX_EVADC_G_REFLAG_REV6_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFLAG_Bits.REV6 */
#define IFX_EVADC_G_REFLAG_REV6_OFF (6u)

/** \brief Length for Ifx_EVADC_G_REFLAG_Bits.REV7 */
#define IFX_EVADC_G_REFLAG_REV7_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFLAG_Bits.REV7 */
#define IFX_EVADC_G_REFLAG_REV7_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFLAG_Bits.REV7 */
#define IFX_EVADC_G_REFLAG_REV7_OFF (7u)

/** \brief Length for Ifx_EVADC_G_REFLAG_Bits.REV8 */
#define IFX_EVADC_G_REFLAG_REV8_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFLAG_Bits.REV8 */
#define IFX_EVADC_G_REFLAG_REV8_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFLAG_Bits.REV8 */
#define IFX_EVADC_G_REFLAG_REV8_OFF (8u)

/** \brief Length for Ifx_EVADC_G_REFLAG_Bits.REV9 */
#define IFX_EVADC_G_REFLAG_REV9_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFLAG_Bits.REV9 */
#define IFX_EVADC_G_REFLAG_REV9_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFLAG_Bits.REV9 */
#define IFX_EVADC_G_REFLAG_REV9_OFF (9u)

/** \brief Length for Ifx_EVADC_G_REFLAG_Bits.REV10 */
#define IFX_EVADC_G_REFLAG_REV10_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFLAG_Bits.REV10 */
#define IFX_EVADC_G_REFLAG_REV10_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFLAG_Bits.REV10 */
#define IFX_EVADC_G_REFLAG_REV10_OFF (10u)

/** \brief Length for Ifx_EVADC_G_REFLAG_Bits.REV11 */
#define IFX_EVADC_G_REFLAG_REV11_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFLAG_Bits.REV11 */
#define IFX_EVADC_G_REFLAG_REV11_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFLAG_Bits.REV11 */
#define IFX_EVADC_G_REFLAG_REV11_OFF (11u)

/** \brief Length for Ifx_EVADC_G_REFLAG_Bits.REV12 */
#define IFX_EVADC_G_REFLAG_REV12_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFLAG_Bits.REV12 */
#define IFX_EVADC_G_REFLAG_REV12_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFLAG_Bits.REV12 */
#define IFX_EVADC_G_REFLAG_REV12_OFF (12u)

/** \brief Length for Ifx_EVADC_G_REFLAG_Bits.REV13 */
#define IFX_EVADC_G_REFLAG_REV13_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFLAG_Bits.REV13 */
#define IFX_EVADC_G_REFLAG_REV13_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFLAG_Bits.REV13 */
#define IFX_EVADC_G_REFLAG_REV13_OFF (13u)

/** \brief Length for Ifx_EVADC_G_REFLAG_Bits.REV14 */
#define IFX_EVADC_G_REFLAG_REV14_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFLAG_Bits.REV14 */
#define IFX_EVADC_G_REFLAG_REV14_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFLAG_Bits.REV14 */
#define IFX_EVADC_G_REFLAG_REV14_OFF (14u)

/** \brief Length for Ifx_EVADC_G_REFLAG_Bits.REV15 */
#define IFX_EVADC_G_REFLAG_REV15_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFLAG_Bits.REV15 */
#define IFX_EVADC_G_REFLAG_REV15_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFLAG_Bits.REV15 */
#define IFX_EVADC_G_REFLAG_REV15_OFF (15u)

/** \brief Length for Ifx_EVADC_G_SEFLAG_Bits.SEV0 */
#define IFX_EVADC_G_SEFLAG_SEV0_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_SEFLAG_Bits.SEV0 */
#define IFX_EVADC_G_SEFLAG_SEV0_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_SEFLAG_Bits.SEV0 */
#define IFX_EVADC_G_SEFLAG_SEV0_OFF (0u)

/** \brief Length for Ifx_EVADC_G_SEFLAG_Bits.SEV1 */
#define IFX_EVADC_G_SEFLAG_SEV1_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_SEFLAG_Bits.SEV1 */
#define IFX_EVADC_G_SEFLAG_SEV1_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_SEFLAG_Bits.SEV1 */
#define IFX_EVADC_G_SEFLAG_SEV1_OFF (1u)

/** \brief Length for Ifx_EVADC_G_SEFLAG_Bits.SEV2 */
#define IFX_EVADC_G_SEFLAG_SEV2_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_SEFLAG_Bits.SEV2 */
#define IFX_EVADC_G_SEFLAG_SEV2_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_SEFLAG_Bits.SEV2 */
#define IFX_EVADC_G_SEFLAG_SEV2_OFF (2u)

/** \brief Length for Ifx_EVADC_G_CEFCLR_Bits.CEV0 */
#define IFX_EVADC_G_CEFCLR_CEV0_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFCLR_Bits.CEV0 */
#define IFX_EVADC_G_CEFCLR_CEV0_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFCLR_Bits.CEV0 */
#define IFX_EVADC_G_CEFCLR_CEV0_OFF (0u)

/** \brief Length for Ifx_EVADC_G_CEFCLR_Bits.CEV1 */
#define IFX_EVADC_G_CEFCLR_CEV1_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFCLR_Bits.CEV1 */
#define IFX_EVADC_G_CEFCLR_CEV1_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFCLR_Bits.CEV1 */
#define IFX_EVADC_G_CEFCLR_CEV1_OFF (1u)

/** \brief Length for Ifx_EVADC_G_CEFCLR_Bits.CEV2 */
#define IFX_EVADC_G_CEFCLR_CEV2_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFCLR_Bits.CEV2 */
#define IFX_EVADC_G_CEFCLR_CEV2_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFCLR_Bits.CEV2 */
#define IFX_EVADC_G_CEFCLR_CEV2_OFF (2u)

/** \brief Length for Ifx_EVADC_G_CEFCLR_Bits.CEV3 */
#define IFX_EVADC_G_CEFCLR_CEV3_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFCLR_Bits.CEV3 */
#define IFX_EVADC_G_CEFCLR_CEV3_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFCLR_Bits.CEV3 */
#define IFX_EVADC_G_CEFCLR_CEV3_OFF (3u)

/** \brief Length for Ifx_EVADC_G_CEFCLR_Bits.CEV4 */
#define IFX_EVADC_G_CEFCLR_CEV4_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFCLR_Bits.CEV4 */
#define IFX_EVADC_G_CEFCLR_CEV4_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFCLR_Bits.CEV4 */
#define IFX_EVADC_G_CEFCLR_CEV4_OFF (4u)

/** \brief Length for Ifx_EVADC_G_CEFCLR_Bits.CEV5 */
#define IFX_EVADC_G_CEFCLR_CEV5_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFCLR_Bits.CEV5 */
#define IFX_EVADC_G_CEFCLR_CEV5_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFCLR_Bits.CEV5 */
#define IFX_EVADC_G_CEFCLR_CEV5_OFF (5u)

/** \brief Length for Ifx_EVADC_G_CEFCLR_Bits.CEV6 */
#define IFX_EVADC_G_CEFCLR_CEV6_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFCLR_Bits.CEV6 */
#define IFX_EVADC_G_CEFCLR_CEV6_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFCLR_Bits.CEV6 */
#define IFX_EVADC_G_CEFCLR_CEV6_OFF (6u)

/** \brief Length for Ifx_EVADC_G_CEFCLR_Bits.CEV7 */
#define IFX_EVADC_G_CEFCLR_CEV7_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFCLR_Bits.CEV7 */
#define IFX_EVADC_G_CEFCLR_CEV7_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFCLR_Bits.CEV7 */
#define IFX_EVADC_G_CEFCLR_CEV7_OFF (7u)

/** \brief Length for Ifx_EVADC_G_CEFCLR_Bits.CEV8 */
#define IFX_EVADC_G_CEFCLR_CEV8_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFCLR_Bits.CEV8 */
#define IFX_EVADC_G_CEFCLR_CEV8_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFCLR_Bits.CEV8 */
#define IFX_EVADC_G_CEFCLR_CEV8_OFF (8u)

/** \brief Length for Ifx_EVADC_G_CEFCLR_Bits.CEV9 */
#define IFX_EVADC_G_CEFCLR_CEV9_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFCLR_Bits.CEV9 */
#define IFX_EVADC_G_CEFCLR_CEV9_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFCLR_Bits.CEV9 */
#define IFX_EVADC_G_CEFCLR_CEV9_OFF (9u)

/** \brief Length for Ifx_EVADC_G_CEFCLR_Bits.CEV10 */
#define IFX_EVADC_G_CEFCLR_CEV10_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFCLR_Bits.CEV10 */
#define IFX_EVADC_G_CEFCLR_CEV10_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFCLR_Bits.CEV10 */
#define IFX_EVADC_G_CEFCLR_CEV10_OFF (10u)

/** \brief Length for Ifx_EVADC_G_CEFCLR_Bits.CEV11 */
#define IFX_EVADC_G_CEFCLR_CEV11_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFCLR_Bits.CEV11 */
#define IFX_EVADC_G_CEFCLR_CEV11_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFCLR_Bits.CEV11 */
#define IFX_EVADC_G_CEFCLR_CEV11_OFF (11u)

/** \brief Length for Ifx_EVADC_G_CEFCLR_Bits.CEV12 */
#define IFX_EVADC_G_CEFCLR_CEV12_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFCLR_Bits.CEV12 */
#define IFX_EVADC_G_CEFCLR_CEV12_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFCLR_Bits.CEV12 */
#define IFX_EVADC_G_CEFCLR_CEV12_OFF (12u)

/** \brief Length for Ifx_EVADC_G_CEFCLR_Bits.CEV13 */
#define IFX_EVADC_G_CEFCLR_CEV13_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFCLR_Bits.CEV13 */
#define IFX_EVADC_G_CEFCLR_CEV13_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFCLR_Bits.CEV13 */
#define IFX_EVADC_G_CEFCLR_CEV13_OFF (13u)

/** \brief Length for Ifx_EVADC_G_CEFCLR_Bits.CEV14 */
#define IFX_EVADC_G_CEFCLR_CEV14_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFCLR_Bits.CEV14 */
#define IFX_EVADC_G_CEFCLR_CEV14_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFCLR_Bits.CEV14 */
#define IFX_EVADC_G_CEFCLR_CEV14_OFF (14u)

/** \brief Length for Ifx_EVADC_G_CEFCLR_Bits.CEV15 */
#define IFX_EVADC_G_CEFCLR_CEV15_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CEFCLR_Bits.CEV15 */
#define IFX_EVADC_G_CEFCLR_CEV15_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CEFCLR_Bits.CEV15 */
#define IFX_EVADC_G_CEFCLR_CEV15_OFF (15u)

/** \brief Length for Ifx_EVADC_G_REFCLR_Bits.REV0 */
#define IFX_EVADC_G_REFCLR_REV0_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFCLR_Bits.REV0 */
#define IFX_EVADC_G_REFCLR_REV0_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFCLR_Bits.REV0 */
#define IFX_EVADC_G_REFCLR_REV0_OFF (0u)

/** \brief Length for Ifx_EVADC_G_REFCLR_Bits.REV1 */
#define IFX_EVADC_G_REFCLR_REV1_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFCLR_Bits.REV1 */
#define IFX_EVADC_G_REFCLR_REV1_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFCLR_Bits.REV1 */
#define IFX_EVADC_G_REFCLR_REV1_OFF (1u)

/** \brief Length for Ifx_EVADC_G_REFCLR_Bits.REV2 */
#define IFX_EVADC_G_REFCLR_REV2_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFCLR_Bits.REV2 */
#define IFX_EVADC_G_REFCLR_REV2_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFCLR_Bits.REV2 */
#define IFX_EVADC_G_REFCLR_REV2_OFF (2u)

/** \brief Length for Ifx_EVADC_G_REFCLR_Bits.REV3 */
#define IFX_EVADC_G_REFCLR_REV3_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFCLR_Bits.REV3 */
#define IFX_EVADC_G_REFCLR_REV3_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFCLR_Bits.REV3 */
#define IFX_EVADC_G_REFCLR_REV3_OFF (3u)

/** \brief Length for Ifx_EVADC_G_REFCLR_Bits.REV4 */
#define IFX_EVADC_G_REFCLR_REV4_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFCLR_Bits.REV4 */
#define IFX_EVADC_G_REFCLR_REV4_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFCLR_Bits.REV4 */
#define IFX_EVADC_G_REFCLR_REV4_OFF (4u)

/** \brief Length for Ifx_EVADC_G_REFCLR_Bits.REV5 */
#define IFX_EVADC_G_REFCLR_REV5_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFCLR_Bits.REV5 */
#define IFX_EVADC_G_REFCLR_REV5_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFCLR_Bits.REV5 */
#define IFX_EVADC_G_REFCLR_REV5_OFF (5u)

/** \brief Length for Ifx_EVADC_G_REFCLR_Bits.REV6 */
#define IFX_EVADC_G_REFCLR_REV6_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFCLR_Bits.REV6 */
#define IFX_EVADC_G_REFCLR_REV6_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFCLR_Bits.REV6 */
#define IFX_EVADC_G_REFCLR_REV6_OFF (6u)

/** \brief Length for Ifx_EVADC_G_REFCLR_Bits.REV7 */
#define IFX_EVADC_G_REFCLR_REV7_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFCLR_Bits.REV7 */
#define IFX_EVADC_G_REFCLR_REV7_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFCLR_Bits.REV7 */
#define IFX_EVADC_G_REFCLR_REV7_OFF (7u)

/** \brief Length for Ifx_EVADC_G_REFCLR_Bits.REV8 */
#define IFX_EVADC_G_REFCLR_REV8_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFCLR_Bits.REV8 */
#define IFX_EVADC_G_REFCLR_REV8_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFCLR_Bits.REV8 */
#define IFX_EVADC_G_REFCLR_REV8_OFF (8u)

/** \brief Length for Ifx_EVADC_G_REFCLR_Bits.REV9 */
#define IFX_EVADC_G_REFCLR_REV9_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFCLR_Bits.REV9 */
#define IFX_EVADC_G_REFCLR_REV9_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFCLR_Bits.REV9 */
#define IFX_EVADC_G_REFCLR_REV9_OFF (9u)

/** \brief Length for Ifx_EVADC_G_REFCLR_Bits.REV10 */
#define IFX_EVADC_G_REFCLR_REV10_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFCLR_Bits.REV10 */
#define IFX_EVADC_G_REFCLR_REV10_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFCLR_Bits.REV10 */
#define IFX_EVADC_G_REFCLR_REV10_OFF (10u)

/** \brief Length for Ifx_EVADC_G_REFCLR_Bits.REV11 */
#define IFX_EVADC_G_REFCLR_REV11_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFCLR_Bits.REV11 */
#define IFX_EVADC_G_REFCLR_REV11_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFCLR_Bits.REV11 */
#define IFX_EVADC_G_REFCLR_REV11_OFF (11u)

/** \brief Length for Ifx_EVADC_G_REFCLR_Bits.REV12 */
#define IFX_EVADC_G_REFCLR_REV12_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFCLR_Bits.REV12 */
#define IFX_EVADC_G_REFCLR_REV12_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFCLR_Bits.REV12 */
#define IFX_EVADC_G_REFCLR_REV12_OFF (12u)

/** \brief Length for Ifx_EVADC_G_REFCLR_Bits.REV13 */
#define IFX_EVADC_G_REFCLR_REV13_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFCLR_Bits.REV13 */
#define IFX_EVADC_G_REFCLR_REV13_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFCLR_Bits.REV13 */
#define IFX_EVADC_G_REFCLR_REV13_OFF (13u)

/** \brief Length for Ifx_EVADC_G_REFCLR_Bits.REV14 */
#define IFX_EVADC_G_REFCLR_REV14_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFCLR_Bits.REV14 */
#define IFX_EVADC_G_REFCLR_REV14_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFCLR_Bits.REV14 */
#define IFX_EVADC_G_REFCLR_REV14_OFF (14u)

/** \brief Length for Ifx_EVADC_G_REFCLR_Bits.REV15 */
#define IFX_EVADC_G_REFCLR_REV15_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_REFCLR_Bits.REV15 */
#define IFX_EVADC_G_REFCLR_REV15_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_REFCLR_Bits.REV15 */
#define IFX_EVADC_G_REFCLR_REV15_OFF (15u)

/** \brief Length for Ifx_EVADC_G_SEFCLR_Bits.SEV0 */
#define IFX_EVADC_G_SEFCLR_SEV0_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_SEFCLR_Bits.SEV0 */
#define IFX_EVADC_G_SEFCLR_SEV0_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_SEFCLR_Bits.SEV0 */
#define IFX_EVADC_G_SEFCLR_SEV0_OFF (0u)

/** \brief Length for Ifx_EVADC_G_SEFCLR_Bits.SEV1 */
#define IFX_EVADC_G_SEFCLR_SEV1_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_SEFCLR_Bits.SEV1 */
#define IFX_EVADC_G_SEFCLR_SEV1_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_SEFCLR_Bits.SEV1 */
#define IFX_EVADC_G_SEFCLR_SEV1_OFF (1u)

/** \brief Length for Ifx_EVADC_G_SEFCLR_Bits.SEV2 */
#define IFX_EVADC_G_SEFCLR_SEV2_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_SEFCLR_Bits.SEV2 */
#define IFX_EVADC_G_SEFCLR_SEV2_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_SEFCLR_Bits.SEV2 */
#define IFX_EVADC_G_SEFCLR_SEV2_OFF (2u)

/** \brief Length for Ifx_EVADC_G_CEVNP0_Bits.CEV0NP */
#define IFX_EVADC_G_CEVNP0_CEV0NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_CEVNP0_Bits.CEV0NP */
#define IFX_EVADC_G_CEVNP0_CEV0NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_CEVNP0_Bits.CEV0NP */
#define IFX_EVADC_G_CEVNP0_CEV0NP_OFF (0u)

/** \brief Length for Ifx_EVADC_G_CEVNP0_Bits.CEV1NP */
#define IFX_EVADC_G_CEVNP0_CEV1NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_CEVNP0_Bits.CEV1NP */
#define IFX_EVADC_G_CEVNP0_CEV1NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_CEVNP0_Bits.CEV1NP */
#define IFX_EVADC_G_CEVNP0_CEV1NP_OFF (4u)

/** \brief Length for Ifx_EVADC_G_CEVNP0_Bits.CEV2NP */
#define IFX_EVADC_G_CEVNP0_CEV2NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_CEVNP0_Bits.CEV2NP */
#define IFX_EVADC_G_CEVNP0_CEV2NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_CEVNP0_Bits.CEV2NP */
#define IFX_EVADC_G_CEVNP0_CEV2NP_OFF (8u)

/** \brief Length for Ifx_EVADC_G_CEVNP0_Bits.CEV3NP */
#define IFX_EVADC_G_CEVNP0_CEV3NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_CEVNP0_Bits.CEV3NP */
#define IFX_EVADC_G_CEVNP0_CEV3NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_CEVNP0_Bits.CEV3NP */
#define IFX_EVADC_G_CEVNP0_CEV3NP_OFF (12u)

/** \brief Length for Ifx_EVADC_G_CEVNP0_Bits.CEV4NP */
#define IFX_EVADC_G_CEVNP0_CEV4NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_CEVNP0_Bits.CEV4NP */
#define IFX_EVADC_G_CEVNP0_CEV4NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_CEVNP0_Bits.CEV4NP */
#define IFX_EVADC_G_CEVNP0_CEV4NP_OFF (16u)

/** \brief Length for Ifx_EVADC_G_CEVNP0_Bits.CEV5NP */
#define IFX_EVADC_G_CEVNP0_CEV5NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_CEVNP0_Bits.CEV5NP */
#define IFX_EVADC_G_CEVNP0_CEV5NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_CEVNP0_Bits.CEV5NP */
#define IFX_EVADC_G_CEVNP0_CEV5NP_OFF (20u)

/** \brief Length for Ifx_EVADC_G_CEVNP0_Bits.CEV6NP */
#define IFX_EVADC_G_CEVNP0_CEV6NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_CEVNP0_Bits.CEV6NP */
#define IFX_EVADC_G_CEVNP0_CEV6NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_CEVNP0_Bits.CEV6NP */
#define IFX_EVADC_G_CEVNP0_CEV6NP_OFF (24u)

/** \brief Length for Ifx_EVADC_G_CEVNP0_Bits.CEV7NP */
#define IFX_EVADC_G_CEVNP0_CEV7NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_CEVNP0_Bits.CEV7NP */
#define IFX_EVADC_G_CEVNP0_CEV7NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_CEVNP0_Bits.CEV7NP */
#define IFX_EVADC_G_CEVNP0_CEV7NP_OFF (28u)

/** \brief Length for Ifx_EVADC_G_CEVNP1_Bits.CEV8NP */
#define IFX_EVADC_G_CEVNP1_CEV8NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_CEVNP1_Bits.CEV8NP */
#define IFX_EVADC_G_CEVNP1_CEV8NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_CEVNP1_Bits.CEV8NP */
#define IFX_EVADC_G_CEVNP1_CEV8NP_OFF (0u)

/** \brief Length for Ifx_EVADC_G_CEVNP1_Bits.CEV9NP */
#define IFX_EVADC_G_CEVNP1_CEV9NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_CEVNP1_Bits.CEV9NP */
#define IFX_EVADC_G_CEVNP1_CEV9NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_CEVNP1_Bits.CEV9NP */
#define IFX_EVADC_G_CEVNP1_CEV9NP_OFF (4u)

/** \brief Length for Ifx_EVADC_G_CEVNP1_Bits.CEV10NP */
#define IFX_EVADC_G_CEVNP1_CEV10NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_CEVNP1_Bits.CEV10NP */
#define IFX_EVADC_G_CEVNP1_CEV10NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_CEVNP1_Bits.CEV10NP */
#define IFX_EVADC_G_CEVNP1_CEV10NP_OFF (8u)

/** \brief Length for Ifx_EVADC_G_CEVNP1_Bits.CEV11NP */
#define IFX_EVADC_G_CEVNP1_CEV11NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_CEVNP1_Bits.CEV11NP */
#define IFX_EVADC_G_CEVNP1_CEV11NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_CEVNP1_Bits.CEV11NP */
#define IFX_EVADC_G_CEVNP1_CEV11NP_OFF (12u)

/** \brief Length for Ifx_EVADC_G_CEVNP1_Bits.CEV12NP */
#define IFX_EVADC_G_CEVNP1_CEV12NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_CEVNP1_Bits.CEV12NP */
#define IFX_EVADC_G_CEVNP1_CEV12NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_CEVNP1_Bits.CEV12NP */
#define IFX_EVADC_G_CEVNP1_CEV12NP_OFF (16u)

/** \brief Length for Ifx_EVADC_G_CEVNP1_Bits.CEV13NP */
#define IFX_EVADC_G_CEVNP1_CEV13NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_CEVNP1_Bits.CEV13NP */
#define IFX_EVADC_G_CEVNP1_CEV13NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_CEVNP1_Bits.CEV13NP */
#define IFX_EVADC_G_CEVNP1_CEV13NP_OFF (20u)

/** \brief Length for Ifx_EVADC_G_CEVNP1_Bits.CEV14NP */
#define IFX_EVADC_G_CEVNP1_CEV14NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_CEVNP1_Bits.CEV14NP */
#define IFX_EVADC_G_CEVNP1_CEV14NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_CEVNP1_Bits.CEV14NP */
#define IFX_EVADC_G_CEVNP1_CEV14NP_OFF (24u)

/** \brief Length for Ifx_EVADC_G_CEVNP1_Bits.CEV15NP */
#define IFX_EVADC_G_CEVNP1_CEV15NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_CEVNP1_Bits.CEV15NP */
#define IFX_EVADC_G_CEVNP1_CEV15NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_CEVNP1_Bits.CEV15NP */
#define IFX_EVADC_G_CEVNP1_CEV15NP_OFF (28u)

/** \brief Length for Ifx_EVADC_G_REVNP0_Bits.REV0NP */
#define IFX_EVADC_G_REVNP0_REV0NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_REVNP0_Bits.REV0NP */
#define IFX_EVADC_G_REVNP0_REV0NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_REVNP0_Bits.REV0NP */
#define IFX_EVADC_G_REVNP0_REV0NP_OFF (0u)

/** \brief Length for Ifx_EVADC_G_REVNP0_Bits.REV1NP */
#define IFX_EVADC_G_REVNP0_REV1NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_REVNP0_Bits.REV1NP */
#define IFX_EVADC_G_REVNP0_REV1NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_REVNP0_Bits.REV1NP */
#define IFX_EVADC_G_REVNP0_REV1NP_OFF (4u)

/** \brief Length for Ifx_EVADC_G_REVNP0_Bits.REV2NP */
#define IFX_EVADC_G_REVNP0_REV2NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_REVNP0_Bits.REV2NP */
#define IFX_EVADC_G_REVNP0_REV2NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_REVNP0_Bits.REV2NP */
#define IFX_EVADC_G_REVNP0_REV2NP_OFF (8u)

/** \brief Length for Ifx_EVADC_G_REVNP0_Bits.REV3NP */
#define IFX_EVADC_G_REVNP0_REV3NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_REVNP0_Bits.REV3NP */
#define IFX_EVADC_G_REVNP0_REV3NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_REVNP0_Bits.REV3NP */
#define IFX_EVADC_G_REVNP0_REV3NP_OFF (12u)

/** \brief Length for Ifx_EVADC_G_REVNP0_Bits.REV4NP */
#define IFX_EVADC_G_REVNP0_REV4NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_REVNP0_Bits.REV4NP */
#define IFX_EVADC_G_REVNP0_REV4NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_REVNP0_Bits.REV4NP */
#define IFX_EVADC_G_REVNP0_REV4NP_OFF (16u)

/** \brief Length for Ifx_EVADC_G_REVNP0_Bits.REV5NP */
#define IFX_EVADC_G_REVNP0_REV5NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_REVNP0_Bits.REV5NP */
#define IFX_EVADC_G_REVNP0_REV5NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_REVNP0_Bits.REV5NP */
#define IFX_EVADC_G_REVNP0_REV5NP_OFF (20u)

/** \brief Length for Ifx_EVADC_G_REVNP0_Bits.REV6NP */
#define IFX_EVADC_G_REVNP0_REV6NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_REVNP0_Bits.REV6NP */
#define IFX_EVADC_G_REVNP0_REV6NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_REVNP0_Bits.REV6NP */
#define IFX_EVADC_G_REVNP0_REV6NP_OFF (24u)

/** \brief Length for Ifx_EVADC_G_REVNP0_Bits.REV7NP */
#define IFX_EVADC_G_REVNP0_REV7NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_REVNP0_Bits.REV7NP */
#define IFX_EVADC_G_REVNP0_REV7NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_REVNP0_Bits.REV7NP */
#define IFX_EVADC_G_REVNP0_REV7NP_OFF (28u)

/** \brief Length for Ifx_EVADC_G_REVNP1_Bits.REV8NP */
#define IFX_EVADC_G_REVNP1_REV8NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_REVNP1_Bits.REV8NP */
#define IFX_EVADC_G_REVNP1_REV8NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_REVNP1_Bits.REV8NP */
#define IFX_EVADC_G_REVNP1_REV8NP_OFF (0u)

/** \brief Length for Ifx_EVADC_G_REVNP1_Bits.REV9NP */
#define IFX_EVADC_G_REVNP1_REV9NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_REVNP1_Bits.REV9NP */
#define IFX_EVADC_G_REVNP1_REV9NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_REVNP1_Bits.REV9NP */
#define IFX_EVADC_G_REVNP1_REV9NP_OFF (4u)

/** \brief Length for Ifx_EVADC_G_REVNP1_Bits.REV10NP */
#define IFX_EVADC_G_REVNP1_REV10NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_REVNP1_Bits.REV10NP */
#define IFX_EVADC_G_REVNP1_REV10NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_REVNP1_Bits.REV10NP */
#define IFX_EVADC_G_REVNP1_REV10NP_OFF (8u)

/** \brief Length for Ifx_EVADC_G_REVNP1_Bits.REV11NP */
#define IFX_EVADC_G_REVNP1_REV11NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_REVNP1_Bits.REV11NP */
#define IFX_EVADC_G_REVNP1_REV11NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_REVNP1_Bits.REV11NP */
#define IFX_EVADC_G_REVNP1_REV11NP_OFF (12u)

/** \brief Length for Ifx_EVADC_G_REVNP1_Bits.REV12NP */
#define IFX_EVADC_G_REVNP1_REV12NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_REVNP1_Bits.REV12NP */
#define IFX_EVADC_G_REVNP1_REV12NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_REVNP1_Bits.REV12NP */
#define IFX_EVADC_G_REVNP1_REV12NP_OFF (16u)

/** \brief Length for Ifx_EVADC_G_REVNP1_Bits.REV13NP */
#define IFX_EVADC_G_REVNP1_REV13NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_REVNP1_Bits.REV13NP */
#define IFX_EVADC_G_REVNP1_REV13NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_REVNP1_Bits.REV13NP */
#define IFX_EVADC_G_REVNP1_REV13NP_OFF (20u)

/** \brief Length for Ifx_EVADC_G_REVNP1_Bits.REV14NP */
#define IFX_EVADC_G_REVNP1_REV14NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_REVNP1_Bits.REV14NP */
#define IFX_EVADC_G_REVNP1_REV14NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_REVNP1_Bits.REV14NP */
#define IFX_EVADC_G_REVNP1_REV14NP_OFF (24u)

/** \brief Length for Ifx_EVADC_G_REVNP1_Bits.REV15NP */
#define IFX_EVADC_G_REVNP1_REV15NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_REVNP1_Bits.REV15NP */
#define IFX_EVADC_G_REVNP1_REV15NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_REVNP1_Bits.REV15NP */
#define IFX_EVADC_G_REVNP1_REV15NP_OFF (28u)

/** \brief Length for Ifx_EVADC_G_SEVNP_Bits.SEV0NP */
#define IFX_EVADC_G_SEVNP_SEV0NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_SEVNP_Bits.SEV0NP */
#define IFX_EVADC_G_SEVNP_SEV0NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_SEVNP_Bits.SEV0NP */
#define IFX_EVADC_G_SEVNP_SEV0NP_OFF (0u)

/** \brief Length for Ifx_EVADC_G_SEVNP_Bits.SEV1NP */
#define IFX_EVADC_G_SEVNP_SEV1NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_SEVNP_Bits.SEV1NP */
#define IFX_EVADC_G_SEVNP_SEV1NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_SEVNP_Bits.SEV1NP */
#define IFX_EVADC_G_SEVNP_SEV1NP_OFF (4u)

/** \brief Length for Ifx_EVADC_G_SEVNP_Bits.SEV2NP */
#define IFX_EVADC_G_SEVNP_SEV2NP_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_SEVNP_Bits.SEV2NP */
#define IFX_EVADC_G_SEVNP_SEV2NP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_SEVNP_Bits.SEV2NP */
#define IFX_EVADC_G_SEVNP_SEV2NP_OFF (8u)

/** \brief Length for Ifx_EVADC_G_SRACT_Bits.AGSR0 */
#define IFX_EVADC_G_SRACT_AGSR0_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_SRACT_Bits.AGSR0 */
#define IFX_EVADC_G_SRACT_AGSR0_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_SRACT_Bits.AGSR0 */
#define IFX_EVADC_G_SRACT_AGSR0_OFF (0u)

/** \brief Length for Ifx_EVADC_G_SRACT_Bits.AGSR1 */
#define IFX_EVADC_G_SRACT_AGSR1_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_SRACT_Bits.AGSR1 */
#define IFX_EVADC_G_SRACT_AGSR1_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_SRACT_Bits.AGSR1 */
#define IFX_EVADC_G_SRACT_AGSR1_OFF (1u)

/** \brief Length for Ifx_EVADC_G_SRACT_Bits.AGSR2 */
#define IFX_EVADC_G_SRACT_AGSR2_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_SRACT_Bits.AGSR2 */
#define IFX_EVADC_G_SRACT_AGSR2_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_SRACT_Bits.AGSR2 */
#define IFX_EVADC_G_SRACT_AGSR2_OFF (2u)

/** \brief Length for Ifx_EVADC_G_SRACT_Bits.AGSR3 */
#define IFX_EVADC_G_SRACT_AGSR3_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_SRACT_Bits.AGSR3 */
#define IFX_EVADC_G_SRACT_AGSR3_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_SRACT_Bits.AGSR3 */
#define IFX_EVADC_G_SRACT_AGSR3_OFF (3u)

/** \brief Length for Ifx_EVADC_G_SRACT_Bits.ASSR0 */
#define IFX_EVADC_G_SRACT_ASSR0_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_SRACT_Bits.ASSR0 */
#define IFX_EVADC_G_SRACT_ASSR0_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_SRACT_Bits.ASSR0 */
#define IFX_EVADC_G_SRACT_ASSR0_OFF (8u)

/** \brief Length for Ifx_EVADC_G_SRACT_Bits.ASSR1 */
#define IFX_EVADC_G_SRACT_ASSR1_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_SRACT_Bits.ASSR1 */
#define IFX_EVADC_G_SRACT_ASSR1_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_SRACT_Bits.ASSR1 */
#define IFX_EVADC_G_SRACT_ASSR1_OFF (9u)

/** \brief Length for Ifx_EVADC_G_SRACT_Bits.ASSR2 */
#define IFX_EVADC_G_SRACT_ASSR2_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_SRACT_Bits.ASSR2 */
#define IFX_EVADC_G_SRACT_ASSR2_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_SRACT_Bits.ASSR2 */
#define IFX_EVADC_G_SRACT_ASSR2_OFF (10u)

/** \brief Length for Ifx_EVADC_G_SRACT_Bits.ASSR3 */
#define IFX_EVADC_G_SRACT_ASSR3_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_SRACT_Bits.ASSR3 */
#define IFX_EVADC_G_SRACT_ASSR3_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_SRACT_Bits.ASSR3 */
#define IFX_EVADC_G_SRACT_ASSR3_OFF (11u)

/** \brief Length for Ifx_EVADC_G_EMUXCTR_Bits.EMUXSET */
#define IFX_EVADC_G_EMUXCTR_EMUXSET_LEN (3u)

/** \brief Mask for Ifx_EVADC_G_EMUXCTR_Bits.EMUXSET */
#define IFX_EVADC_G_EMUXCTR_EMUXSET_MSK (0x7u)

/** \brief Offset for Ifx_EVADC_G_EMUXCTR_Bits.EMUXSET */
#define IFX_EVADC_G_EMUXCTR_EMUXSET_OFF (0u)

/** \brief Length for Ifx_EVADC_G_EMUXCTR_Bits.EMUXMODE */
#define IFX_EVADC_G_EMUXCTR_EMUXMODE_LEN (3u)

/** \brief Mask for Ifx_EVADC_G_EMUXCTR_Bits.EMUXMODE */
#define IFX_EVADC_G_EMUXCTR_EMUXMODE_MSK (0x7u)

/** \brief Offset for Ifx_EVADC_G_EMUXCTR_Bits.EMUXMODE */
#define IFX_EVADC_G_EMUXCTR_EMUXMODE_OFF (4u)

/** \brief Length for Ifx_EVADC_G_EMUXCTR_Bits.EMXCOD */
#define IFX_EVADC_G_EMUXCTR_EMXCOD_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_EMUXCTR_Bits.EMXCOD */
#define IFX_EVADC_G_EMUXCTR_EMXCOD_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_EMUXCTR_Bits.EMXCOD */
#define IFX_EVADC_G_EMUXCTR_EMXCOD_OFF (12u)

/** \brief Length for Ifx_EVADC_G_EMUXCTR_Bits.EMXST */
#define IFX_EVADC_G_EMUXCTR_EMXST_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_EMUXCTR_Bits.EMXST */
#define IFX_EVADC_G_EMUXCTR_EMXST_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_EMUXCTR_Bits.EMXST */
#define IFX_EVADC_G_EMUXCTR_EMXST_OFF (13u)

/** \brief Length for Ifx_EVADC_G_EMUXCTR_Bits.EMXCSS */
#define IFX_EVADC_G_EMUXCTR_EMXCSS_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_EMUXCTR_Bits.EMXCSS */
#define IFX_EVADC_G_EMUXCTR_EMXCSS_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_EMUXCTR_Bits.EMXCSS */
#define IFX_EVADC_G_EMUXCTR_EMXCSS_OFF (14u)

/** \brief Length for Ifx_EVADC_G_EMUXCTR_Bits.EMXWC */
#define IFX_EVADC_G_EMUXCTR_EMXWC_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_EMUXCTR_Bits.EMXWC */
#define IFX_EVADC_G_EMUXCTR_EMXWC_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_EMUXCTR_Bits.EMXWC */
#define IFX_EVADC_G_EMUXCTR_EMXWC_OFF (15u)

/** \brief Length for Ifx_EVADC_G_EMUXCTR_Bits.EMUXACT */
#define IFX_EVADC_G_EMUXCTR_EMUXACT_LEN (3u)

/** \brief Mask for Ifx_EVADC_G_EMUXCTR_Bits.EMUXACT */
#define IFX_EVADC_G_EMUXCTR_EMUXACT_MSK (0x7u)

/** \brief Offset for Ifx_EVADC_G_EMUXCTR_Bits.EMUXACT */
#define IFX_EVADC_G_EMUXCTR_EMUXACT_OFF (16u)

/** \brief Length for Ifx_EVADC_G_EMUXCTR_Bits.EMUXCCB */
#define IFX_EVADC_G_EMUXCTR_EMUXCCB_LEN (5u)

/** \brief Mask for Ifx_EVADC_G_EMUXCTR_Bits.EMUXCCB */
#define IFX_EVADC_G_EMUXCTR_EMUXCCB_MSK (0x1fu)

/** \brief Offset for Ifx_EVADC_G_EMUXCTR_Bits.EMUXCCB */
#define IFX_EVADC_G_EMUXCTR_EMUXCCB_OFF (20u)

/** \brief Length for Ifx_EVADC_G_EMUXCS_Bits.EMUXCH */
#define IFX_EVADC_G_EMUXCS_EMUXCH_LEN (16u)

/** \brief Mask for Ifx_EVADC_G_EMUXCS_Bits.EMUXCH */
#define IFX_EVADC_G_EMUXCS_EMUXCH_MSK (0xffffu)

/** \brief Offset for Ifx_EVADC_G_EMUXCS_Bits.EMUXCH */
#define IFX_EVADC_G_EMUXCS_EMUXCH_OFF (0u)

/** \brief Length for Ifx_EVADC_G_VFR_Bits.VF0 */
#define IFX_EVADC_G_VFR_VF0_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_VFR_Bits.VF0 */
#define IFX_EVADC_G_VFR_VF0_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_VFR_Bits.VF0 */
#define IFX_EVADC_G_VFR_VF0_OFF (0u)

/** \brief Length for Ifx_EVADC_G_VFR_Bits.VF1 */
#define IFX_EVADC_G_VFR_VF1_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_VFR_Bits.VF1 */
#define IFX_EVADC_G_VFR_VF1_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_VFR_Bits.VF1 */
#define IFX_EVADC_G_VFR_VF1_OFF (1u)

/** \brief Length for Ifx_EVADC_G_VFR_Bits.VF2 */
#define IFX_EVADC_G_VFR_VF2_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_VFR_Bits.VF2 */
#define IFX_EVADC_G_VFR_VF2_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_VFR_Bits.VF2 */
#define IFX_EVADC_G_VFR_VF2_OFF (2u)

/** \brief Length for Ifx_EVADC_G_VFR_Bits.VF3 */
#define IFX_EVADC_G_VFR_VF3_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_VFR_Bits.VF3 */
#define IFX_EVADC_G_VFR_VF3_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_VFR_Bits.VF3 */
#define IFX_EVADC_G_VFR_VF3_OFF (3u)

/** \brief Length for Ifx_EVADC_G_VFR_Bits.VF4 */
#define IFX_EVADC_G_VFR_VF4_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_VFR_Bits.VF4 */
#define IFX_EVADC_G_VFR_VF4_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_VFR_Bits.VF4 */
#define IFX_EVADC_G_VFR_VF4_OFF (4u)

/** \brief Length for Ifx_EVADC_G_VFR_Bits.VF5 */
#define IFX_EVADC_G_VFR_VF5_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_VFR_Bits.VF5 */
#define IFX_EVADC_G_VFR_VF5_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_VFR_Bits.VF5 */
#define IFX_EVADC_G_VFR_VF5_OFF (5u)

/** \brief Length for Ifx_EVADC_G_VFR_Bits.VF6 */
#define IFX_EVADC_G_VFR_VF6_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_VFR_Bits.VF6 */
#define IFX_EVADC_G_VFR_VF6_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_VFR_Bits.VF6 */
#define IFX_EVADC_G_VFR_VF6_OFF (6u)

/** \brief Length for Ifx_EVADC_G_VFR_Bits.VF7 */
#define IFX_EVADC_G_VFR_VF7_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_VFR_Bits.VF7 */
#define IFX_EVADC_G_VFR_VF7_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_VFR_Bits.VF7 */
#define IFX_EVADC_G_VFR_VF7_OFF (7u)

/** \brief Length for Ifx_EVADC_G_VFR_Bits.VF8 */
#define IFX_EVADC_G_VFR_VF8_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_VFR_Bits.VF8 */
#define IFX_EVADC_G_VFR_VF8_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_VFR_Bits.VF8 */
#define IFX_EVADC_G_VFR_VF8_OFF (8u)

/** \brief Length for Ifx_EVADC_G_VFR_Bits.VF9 */
#define IFX_EVADC_G_VFR_VF9_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_VFR_Bits.VF9 */
#define IFX_EVADC_G_VFR_VF9_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_VFR_Bits.VF9 */
#define IFX_EVADC_G_VFR_VF9_OFF (9u)

/** \brief Length for Ifx_EVADC_G_VFR_Bits.VF10 */
#define IFX_EVADC_G_VFR_VF10_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_VFR_Bits.VF10 */
#define IFX_EVADC_G_VFR_VF10_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_VFR_Bits.VF10 */
#define IFX_EVADC_G_VFR_VF10_OFF (10u)

/** \brief Length for Ifx_EVADC_G_VFR_Bits.VF11 */
#define IFX_EVADC_G_VFR_VF11_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_VFR_Bits.VF11 */
#define IFX_EVADC_G_VFR_VF11_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_VFR_Bits.VF11 */
#define IFX_EVADC_G_VFR_VF11_OFF (11u)

/** \brief Length for Ifx_EVADC_G_VFR_Bits.VF12 */
#define IFX_EVADC_G_VFR_VF12_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_VFR_Bits.VF12 */
#define IFX_EVADC_G_VFR_VF12_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_VFR_Bits.VF12 */
#define IFX_EVADC_G_VFR_VF12_OFF (12u)

/** \brief Length for Ifx_EVADC_G_VFR_Bits.VF13 */
#define IFX_EVADC_G_VFR_VF13_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_VFR_Bits.VF13 */
#define IFX_EVADC_G_VFR_VF13_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_VFR_Bits.VF13 */
#define IFX_EVADC_G_VFR_VF13_OFF (13u)

/** \brief Length for Ifx_EVADC_G_VFR_Bits.VF14 */
#define IFX_EVADC_G_VFR_VF14_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_VFR_Bits.VF14 */
#define IFX_EVADC_G_VFR_VF14_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_VFR_Bits.VF14 */
#define IFX_EVADC_G_VFR_VF14_OFF (14u)

/** \brief Length for Ifx_EVADC_G_VFR_Bits.VF15 */
#define IFX_EVADC_G_VFR_VF15_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_VFR_Bits.VF15 */
#define IFX_EVADC_G_VFR_VF15_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_VFR_Bits.VF15 */
#define IFX_EVADC_G_VFR_VF15_OFF (15u)

/** \brief Length for Ifx_EVADC_G_CHCTR_Bits.ICLSEL */
#define IFX_EVADC_G_CHCTR_ICLSEL_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_CHCTR_Bits.ICLSEL */
#define IFX_EVADC_G_CHCTR_ICLSEL_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_CHCTR_Bits.ICLSEL */
#define IFX_EVADC_G_CHCTR_ICLSEL_OFF (0u)

/** \brief Length for Ifx_EVADC_G_CHCTR_Bits.BNDSELL */
#define IFX_EVADC_G_CHCTR_BNDSELL_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_CHCTR_Bits.BNDSELL */
#define IFX_EVADC_G_CHCTR_BNDSELL_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_CHCTR_Bits.BNDSELL */
#define IFX_EVADC_G_CHCTR_BNDSELL_OFF (4u)

/** \brief Length for Ifx_EVADC_G_CHCTR_Bits.BNDSELU */
#define IFX_EVADC_G_CHCTR_BNDSELU_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_CHCTR_Bits.BNDSELU */
#define IFX_EVADC_G_CHCTR_BNDSELU_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_CHCTR_Bits.BNDSELU */
#define IFX_EVADC_G_CHCTR_BNDSELU_OFF (6u)

/** \brief Length for Ifx_EVADC_G_CHCTR_Bits.CHEVMODE */
#define IFX_EVADC_G_CHCTR_CHEVMODE_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_CHCTR_Bits.CHEVMODE */
#define IFX_EVADC_G_CHCTR_CHEVMODE_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_CHCTR_Bits.CHEVMODE */
#define IFX_EVADC_G_CHCTR_CHEVMODE_OFF (8u)

/** \brief Length for Ifx_EVADC_G_CHCTR_Bits.SYNC */
#define IFX_EVADC_G_CHCTR_SYNC_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CHCTR_Bits.SYNC */
#define IFX_EVADC_G_CHCTR_SYNC_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CHCTR_Bits.SYNC */
#define IFX_EVADC_G_CHCTR_SYNC_OFF (10u)

/** \brief Length for Ifx_EVADC_G_CHCTR_Bits.REFSEL */
#define IFX_EVADC_G_CHCTR_REFSEL_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CHCTR_Bits.REFSEL */
#define IFX_EVADC_G_CHCTR_REFSEL_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CHCTR_Bits.REFSEL */
#define IFX_EVADC_G_CHCTR_REFSEL_OFF (11u)

/** \brief Length for Ifx_EVADC_G_CHCTR_Bits.BNDSELX */
#define IFX_EVADC_G_CHCTR_BNDSELX_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_CHCTR_Bits.BNDSELX */
#define IFX_EVADC_G_CHCTR_BNDSELX_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_CHCTR_Bits.BNDSELX */
#define IFX_EVADC_G_CHCTR_BNDSELX_OFF (12u)

/** \brief Length for Ifx_EVADC_G_CHCTR_Bits.RESREG */
#define IFX_EVADC_G_CHCTR_RESREG_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_CHCTR_Bits.RESREG */
#define IFX_EVADC_G_CHCTR_RESREG_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_CHCTR_Bits.RESREG */
#define IFX_EVADC_G_CHCTR_RESREG_OFF (16u)

/** \brief Length for Ifx_EVADC_G_CHCTR_Bits.RESTGT */
#define IFX_EVADC_G_CHCTR_RESTGT_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CHCTR_Bits.RESTGT */
#define IFX_EVADC_G_CHCTR_RESTGT_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CHCTR_Bits.RESTGT */
#define IFX_EVADC_G_CHCTR_RESTGT_OFF (20u)

/** \brief Length for Ifx_EVADC_G_CHCTR_Bits.RESPOS */
#define IFX_EVADC_G_CHCTR_RESPOS_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CHCTR_Bits.RESPOS */
#define IFX_EVADC_G_CHCTR_RESPOS_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CHCTR_Bits.RESPOS */
#define IFX_EVADC_G_CHCTR_RESPOS_OFF (21u)

/** \brief Length for Ifx_EVADC_G_CHCTR_Bits.BWDCH */
#define IFX_EVADC_G_CHCTR_BWDCH_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_CHCTR_Bits.BWDCH */
#define IFX_EVADC_G_CHCTR_BWDCH_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_CHCTR_Bits.BWDCH */
#define IFX_EVADC_G_CHCTR_BWDCH_OFF (28u)

/** \brief Length for Ifx_EVADC_G_CHCTR_Bits.BWDEN */
#define IFX_EVADC_G_CHCTR_BWDEN_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_CHCTR_Bits.BWDEN */
#define IFX_EVADC_G_CHCTR_BWDEN_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_CHCTR_Bits.BWDEN */
#define IFX_EVADC_G_CHCTR_BWDEN_OFF (30u)

/** \brief Length for Ifx_EVADC_G_RCR_Bits.DRCTR */
#define IFX_EVADC_G_RCR_DRCTR_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_RCR_Bits.DRCTR */
#define IFX_EVADC_G_RCR_DRCTR_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_RCR_Bits.DRCTR */
#define IFX_EVADC_G_RCR_DRCTR_OFF (16u)

/** \brief Length for Ifx_EVADC_G_RCR_Bits.DMM */
#define IFX_EVADC_G_RCR_DMM_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_RCR_Bits.DMM */
#define IFX_EVADC_G_RCR_DMM_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_RCR_Bits.DMM */
#define IFX_EVADC_G_RCR_DMM_OFF (20u)

/** \brief Length for Ifx_EVADC_G_RCR_Bits.WFR */
#define IFX_EVADC_G_RCR_WFR_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_RCR_Bits.WFR */
#define IFX_EVADC_G_RCR_WFR_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_RCR_Bits.WFR */
#define IFX_EVADC_G_RCR_WFR_OFF (24u)

/** \brief Length for Ifx_EVADC_G_RCR_Bits.FEN */
#define IFX_EVADC_G_RCR_FEN_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_RCR_Bits.FEN */
#define IFX_EVADC_G_RCR_FEN_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_RCR_Bits.FEN */
#define IFX_EVADC_G_RCR_FEN_OFF (25u)

/** \brief Length for Ifx_EVADC_G_RCR_Bits.SRGEN */
#define IFX_EVADC_G_RCR_SRGEN_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_RCR_Bits.SRGEN */
#define IFX_EVADC_G_RCR_SRGEN_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_RCR_Bits.SRGEN */
#define IFX_EVADC_G_RCR_SRGEN_OFF (31u)

/** \brief Length for Ifx_EVADC_G_RES_Bits.RESULT */
#define IFX_EVADC_G_RES_RESULT_LEN (16u)

/** \brief Mask for Ifx_EVADC_G_RES_Bits.RESULT */
#define IFX_EVADC_G_RES_RESULT_MSK (0xffffu)

/** \brief Offset for Ifx_EVADC_G_RES_Bits.RESULT */
#define IFX_EVADC_G_RES_RESULT_OFF (0u)

/** \brief Length for Ifx_EVADC_G_RES_Bits.DRC */
#define IFX_EVADC_G_RES_DRC_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_RES_Bits.DRC */
#define IFX_EVADC_G_RES_DRC_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_RES_Bits.DRC */
#define IFX_EVADC_G_RES_DRC_OFF (16u)

/** \brief Length for Ifx_EVADC_G_RES_Bits.CHNR */
#define IFX_EVADC_G_RES_CHNR_LEN (5u)

/** \brief Mask for Ifx_EVADC_G_RES_Bits.CHNR */
#define IFX_EVADC_G_RES_CHNR_MSK (0x1fu)

/** \brief Offset for Ifx_EVADC_G_RES_Bits.CHNR */
#define IFX_EVADC_G_RES_CHNR_OFF (20u)

/** \brief Length for Ifx_EVADC_G_RES_Bits.EMUX */
#define IFX_EVADC_G_RES_EMUX_LEN (3u)

/** \brief Mask for Ifx_EVADC_G_RES_Bits.EMUX */
#define IFX_EVADC_G_RES_EMUX_MSK (0x7u)

/** \brief Offset for Ifx_EVADC_G_RES_Bits.EMUX */
#define IFX_EVADC_G_RES_EMUX_OFF (25u)

/** \brief Length for Ifx_EVADC_G_RES_Bits.CRS */
#define IFX_EVADC_G_RES_CRS_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_RES_Bits.CRS */
#define IFX_EVADC_G_RES_CRS_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_RES_Bits.CRS */
#define IFX_EVADC_G_RES_CRS_OFF (28u)

/** \brief Length for Ifx_EVADC_G_RES_Bits.VF */
#define IFX_EVADC_G_RES_VF_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_RES_Bits.VF */
#define IFX_EVADC_G_RES_VF_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_RES_Bits.VF */
#define IFX_EVADC_G_RES_VF_OFF (31u)

/** \brief Length for Ifx_EVADC_G_RESD_Bits.RESULT */
#define IFX_EVADC_G_RESD_RESULT_LEN (16u)

/** \brief Mask for Ifx_EVADC_G_RESD_Bits.RESULT */
#define IFX_EVADC_G_RESD_RESULT_MSK (0xffffu)

/** \brief Offset for Ifx_EVADC_G_RESD_Bits.RESULT */
#define IFX_EVADC_G_RESD_RESULT_OFF (0u)

/** \brief Length for Ifx_EVADC_G_RESD_Bits.DRC */
#define IFX_EVADC_G_RESD_DRC_LEN (4u)

/** \brief Mask for Ifx_EVADC_G_RESD_Bits.DRC */
#define IFX_EVADC_G_RESD_DRC_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_G_RESD_Bits.DRC */
#define IFX_EVADC_G_RESD_DRC_OFF (16u)

/** \brief Length for Ifx_EVADC_G_RESD_Bits.CHNR */
#define IFX_EVADC_G_RESD_CHNR_LEN (5u)

/** \brief Mask for Ifx_EVADC_G_RESD_Bits.CHNR */
#define IFX_EVADC_G_RESD_CHNR_MSK (0x1fu)

/** \brief Offset for Ifx_EVADC_G_RESD_Bits.CHNR */
#define IFX_EVADC_G_RESD_CHNR_OFF (20u)

/** \brief Length for Ifx_EVADC_G_RESD_Bits.EMUX */
#define IFX_EVADC_G_RESD_EMUX_LEN (3u)

/** \brief Mask for Ifx_EVADC_G_RESD_Bits.EMUX */
#define IFX_EVADC_G_RESD_EMUX_MSK (0x7u)

/** \brief Offset for Ifx_EVADC_G_RESD_Bits.EMUX */
#define IFX_EVADC_G_RESD_EMUX_OFF (25u)

/** \brief Length for Ifx_EVADC_G_RESD_Bits.CRS */
#define IFX_EVADC_G_RESD_CRS_LEN (2u)

/** \brief Mask for Ifx_EVADC_G_RESD_Bits.CRS */
#define IFX_EVADC_G_RESD_CRS_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_G_RESD_Bits.CRS */
#define IFX_EVADC_G_RESD_CRS_OFF (28u)

/** \brief Length for Ifx_EVADC_G_RESD_Bits.VF */
#define IFX_EVADC_G_RESD_VF_LEN (1u)

/** \brief Mask for Ifx_EVADC_G_RESD_Bits.VF */
#define IFX_EVADC_G_RESD_VF_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_G_RESD_Bits.VF */
#define IFX_EVADC_G_RESD_VF_OFF (31u)

/** \brief Length for Ifx_EVADC_FC_FCCTRL_Bits.STCF */
#define IFX_EVADC_FC_FCCTRL_STCF_LEN (5u)

/** \brief Mask for Ifx_EVADC_FC_FCCTRL_Bits.STCF */
#define IFX_EVADC_FC_FCCTRL_STCF_MSK (0x1fu)

/** \brief Offset for Ifx_EVADC_FC_FCCTRL_Bits.STCF */
#define IFX_EVADC_FC_FCCTRL_STCF_OFF (0u)

/** \brief Length for Ifx_EVADC_FC_FCCTRL_Bits.RPE */
#define IFX_EVADC_FC_FCCTRL_RPE_LEN (1u)

/** \brief Mask for Ifx_EVADC_FC_FCCTRL_Bits.RPE */
#define IFX_EVADC_FC_FCCTRL_RPE_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_FC_FCCTRL_Bits.RPE */
#define IFX_EVADC_FC_FCCTRL_RPE_OFF (5u)

/** \brief Length for Ifx_EVADC_FC_FCCTRL_Bits.AIPF */
#define IFX_EVADC_FC_FCCTRL_AIPF_LEN (2u)

/** \brief Mask for Ifx_EVADC_FC_FCCTRL_Bits.AIPF */
#define IFX_EVADC_FC_FCCTRL_AIPF_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_FC_FCCTRL_Bits.AIPF */
#define IFX_EVADC_FC_FCCTRL_AIPF_OFF (6u)

/** \brief Length for Ifx_EVADC_FC_FCCTRL_Bits.CHEVMODE */
#define IFX_EVADC_FC_FCCTRL_CHEVMODE_LEN (2u)

/** \brief Mask for Ifx_EVADC_FC_FCCTRL_Bits.CHEVMODE */
#define IFX_EVADC_FC_FCCTRL_CHEVMODE_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_FC_FCCTRL_Bits.CHEVMODE */
#define IFX_EVADC_FC_FCCTRL_CHEVMODE_OFF (8u)

/** \brief Length for Ifx_EVADC_FC_FCCTRL_Bits.DIVA */
#define IFX_EVADC_FC_FCCTRL_DIVA_LEN (5u)

/** \brief Mask for Ifx_EVADC_FC_FCCTRL_Bits.DIVA */
#define IFX_EVADC_FC_FCCTRL_DIVA_MSK (0x1fu)

/** \brief Offset for Ifx_EVADC_FC_FCCTRL_Bits.DIVA */
#define IFX_EVADC_FC_FCCTRL_DIVA_OFF (10u)

/** \brief Length for Ifx_EVADC_FC_FCCTRL_Bits.CPWC */
#define IFX_EVADC_FC_FCCTRL_CPWC_LEN (1u)

/** \brief Mask for Ifx_EVADC_FC_FCCTRL_Bits.CPWC */
#define IFX_EVADC_FC_FCCTRL_CPWC_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_FC_FCCTRL_Bits.CPWC */
#define IFX_EVADC_FC_FCCTRL_CPWC_OFF (15u)

/** \brief Length for Ifx_EVADC_FC_FCCTRL_Bits.XTSEL */
#define IFX_EVADC_FC_FCCTRL_XTSEL_LEN (4u)

/** \brief Mask for Ifx_EVADC_FC_FCCTRL_Bits.XTSEL */
#define IFX_EVADC_FC_FCCTRL_XTSEL_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_FC_FCCTRL_Bits.XTSEL */
#define IFX_EVADC_FC_FCCTRL_XTSEL_OFF (16u)

/** \brief Length for Ifx_EVADC_FC_FCCTRL_Bits.XTLVL */
#define IFX_EVADC_FC_FCCTRL_XTLVL_LEN (1u)

/** \brief Mask for Ifx_EVADC_FC_FCCTRL_Bits.XTLVL */
#define IFX_EVADC_FC_FCCTRL_XTLVL_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_FC_FCCTRL_Bits.XTLVL */
#define IFX_EVADC_FC_FCCTRL_XTLVL_OFF (20u)

/** \brief Length for Ifx_EVADC_FC_FCCTRL_Bits.XTMODE */
#define IFX_EVADC_FC_FCCTRL_XTMODE_LEN (2u)

/** \brief Mask for Ifx_EVADC_FC_FCCTRL_Bits.XTMODE */
#define IFX_EVADC_FC_FCCTRL_XTMODE_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_FC_FCCTRL_Bits.XTMODE */
#define IFX_EVADC_FC_FCCTRL_XTMODE_OFF (21u)

/** \brief Length for Ifx_EVADC_FC_FCCTRL_Bits.XTPOL */
#define IFX_EVADC_FC_FCCTRL_XTPOL_LEN (1u)

/** \brief Mask for Ifx_EVADC_FC_FCCTRL_Bits.XTPOL */
#define IFX_EVADC_FC_FCCTRL_XTPOL_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_FC_FCCTRL_Bits.XTPOL */
#define IFX_EVADC_FC_FCCTRL_XTPOL_OFF (23u)

/** \brief Length for Ifx_EVADC_FC_FCCTRL_Bits.GTMODE */
#define IFX_EVADC_FC_FCCTRL_GTMODE_LEN (2u)

/** \brief Mask for Ifx_EVADC_FC_FCCTRL_Bits.GTMODE */
#define IFX_EVADC_FC_FCCTRL_GTMODE_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_FC_FCCTRL_Bits.GTMODE */
#define IFX_EVADC_FC_FCCTRL_GTMODE_OFF (24u)

/** \brief Length for Ifx_EVADC_FC_FCCTRL_Bits.FCCHNR */
#define IFX_EVADC_FC_FCCTRL_FCCHNR_LEN (5u)

/** \brief Mask for Ifx_EVADC_FC_FCCTRL_Bits.FCCHNR */
#define IFX_EVADC_FC_FCCTRL_FCCHNR_MSK (0x1fu)

/** \brief Offset for Ifx_EVADC_FC_FCCTRL_Bits.FCCHNR */
#define IFX_EVADC_FC_FCCTRL_FCCHNR_OFF (26u)

/** \brief Length for Ifx_EVADC_FC_FCCTRL_Bits.XTWC */
#define IFX_EVADC_FC_FCCTRL_XTWC_LEN (1u)

/** \brief Mask for Ifx_EVADC_FC_FCCTRL_Bits.XTWC */
#define IFX_EVADC_FC_FCCTRL_XTWC_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_FC_FCCTRL_Bits.XTWC */
#define IFX_EVADC_FC_FCCTRL_XTWC_OFF (31u)

/** \brief Length for Ifx_EVADC_FC_FCM_Bits.RUNCOMP */
#define IFX_EVADC_FC_FCM_RUNCOMP_LEN (2u)

/** \brief Mask for Ifx_EVADC_FC_FCM_Bits.RUNCOMP */
#define IFX_EVADC_FC_FCM_RUNCOMP_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_FC_FCM_Bits.RUNCOMP */
#define IFX_EVADC_FC_FCM_RUNCOMP_OFF (0u)

/** \brief Length for Ifx_EVADC_FC_FCM_Bits.RUNRAMP */
#define IFX_EVADC_FC_FCM_RUNRAMP_LEN (2u)

/** \brief Mask for Ifx_EVADC_FC_FCM_Bits.RUNRAMP */
#define IFX_EVADC_FC_FCM_RUNRAMP_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_FC_FCM_Bits.RUNRAMP */
#define IFX_EVADC_FC_FCM_RUNRAMP_OFF (2u)

/** \brief Length for Ifx_EVADC_FC_FCM_Bits.FCRDIR */
#define IFX_EVADC_FC_FCM_FCRDIR_LEN (1u)

/** \brief Mask for Ifx_EVADC_FC_FCM_Bits.FCRDIR */
#define IFX_EVADC_FC_FCM_FCRDIR_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_FC_FCM_Bits.FCRDIR */
#define IFX_EVADC_FC_FCM_FCRDIR_OFF (4u)

/** \brief Length for Ifx_EVADC_FC_FCM_Bits.ANON */
#define IFX_EVADC_FC_FCM_ANON_LEN (1u)

/** \brief Mask for Ifx_EVADC_FC_FCM_Bits.ANON */
#define IFX_EVADC_FC_FCM_ANON_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_FC_FCM_Bits.ANON */
#define IFX_EVADC_FC_FCM_ANON_OFF (5u)

/** \brief Length for Ifx_EVADC_FC_FCM_Bits.ACSD */
#define IFX_EVADC_FC_FCM_ACSD_LEN (2u)

/** \brief Mask for Ifx_EVADC_FC_FCM_Bits.ACSD */
#define IFX_EVADC_FC_FCM_ACSD_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_FC_FCM_Bits.ACSD */
#define IFX_EVADC_FC_FCM_ACSD_OFF (6u)

/** \brief Length for Ifx_EVADC_FC_FCM_Bits.FCTRIV */
#define IFX_EVADC_FC_FCM_FCTRIV_LEN (8u)

/** \brief Mask for Ifx_EVADC_FC_FCM_Bits.FCTRIV */
#define IFX_EVADC_FC_FCM_FCTRIV_MSK (0xffu)

/** \brief Offset for Ifx_EVADC_FC_FCM_Bits.FCTRIV */
#define IFX_EVADC_FC_FCM_FCTRIV_OFF (8u)

/** \brief Length for Ifx_EVADC_FC_FCM_Bits.SRG */
#define IFX_EVADC_FC_FCM_SRG_LEN (2u)

/** \brief Mask for Ifx_EVADC_FC_FCM_Bits.SRG */
#define IFX_EVADC_FC_FCM_SRG_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_FC_FCM_Bits.SRG */
#define IFX_EVADC_FC_FCM_SRG_OFF (16u)

/** \brief Length for Ifx_EVADC_FC_FCM_Bits.AUE */
#define IFX_EVADC_FC_FCM_AUE_LEN (2u)

/** \brief Mask for Ifx_EVADC_FC_FCM_Bits.AUE */
#define IFX_EVADC_FC_FCM_AUE_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_FC_FCM_Bits.AUE */
#define IFX_EVADC_FC_FCM_AUE_OFF (18u)

/** \brief Length for Ifx_EVADC_FC_FCM_Bits.SSE */
#define IFX_EVADC_FC_FCM_SSE_LEN (1u)

/** \brief Mask for Ifx_EVADC_FC_FCM_Bits.SSE */
#define IFX_EVADC_FC_FCM_SSE_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_FC_FCM_Bits.SSE */
#define IFX_EVADC_FC_FCM_SSE_OFF (20u)

/** \brief Length for Ifx_EVADC_FC_FCM_Bits.FCMWC */
#define IFX_EVADC_FC_FCM_FCMWC_LEN (1u)

/** \brief Mask for Ifx_EVADC_FC_FCM_Bits.FCMWC */
#define IFX_EVADC_FC_FCM_FCMWC_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_FC_FCM_Bits.FCMWC */
#define IFX_EVADC_FC_FCM_FCMWC_OFF (21u)

/** \brief Length for Ifx_EVADC_FC_FCM_Bits.FCREF */
#define IFX_EVADC_FC_FCM_FCREF_LEN (10u)

/** \brief Mask for Ifx_EVADC_FC_FCM_Bits.FCREF */
#define IFX_EVADC_FC_FCM_FCREF_MSK (0x3ffu)

/** \brief Offset for Ifx_EVADC_FC_FCM_Bits.FCREF */
#define IFX_EVADC_FC_FCM_FCREF_OFF (22u)

/** \brief Length for Ifx_EVADC_FC_FCRAMP0_Bits.FCRCOMPA */
#define IFX_EVADC_FC_FCRAMP0_FCRCOMPA_LEN (10u)

/** \brief Mask for Ifx_EVADC_FC_FCRAMP0_Bits.FCRCOMPA */
#define IFX_EVADC_FC_FCRAMP0_FCRCOMPA_MSK (0x3ffu)

/** \brief Offset for Ifx_EVADC_FC_FCRAMP0_Bits.FCRCOMPA */
#define IFX_EVADC_FC_FCRAMP0_FCRCOMPA_OFF (0u)

/** \brief Length for Ifx_EVADC_FC_FCRAMP0_Bits.FCRSTEP */
#define IFX_EVADC_FC_FCRAMP0_FCRSTEP_LEN (8u)

/** \brief Mask for Ifx_EVADC_FC_FCRAMP0_Bits.FCRSTEP */
#define IFX_EVADC_FC_FCRAMP0_FCRSTEP_MSK (0xffu)

/** \brief Offset for Ifx_EVADC_FC_FCRAMP0_Bits.FCRSTEP */
#define IFX_EVADC_FC_FCRAMP0_FCRSTEP_OFF (16u)

/** \brief Length for Ifx_EVADC_FC_FCRAMP0_Bits.FSWC */
#define IFX_EVADC_FC_FCRAMP0_FSWC_LEN (1u)

/** \brief Mask for Ifx_EVADC_FC_FCRAMP0_Bits.FSWC */
#define IFX_EVADC_FC_FCRAMP0_FSWC_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_FC_FCRAMP0_Bits.FSWC */
#define IFX_EVADC_FC_FCRAMP0_FSWC_OFF (31u)

/** \brief Length for Ifx_EVADC_FC_FCRAMP1_Bits.FCRCOMPB */
#define IFX_EVADC_FC_FCRAMP1_FCRCOMPB_LEN (10u)

/** \brief Mask for Ifx_EVADC_FC_FCRAMP1_Bits.FCRCOMPB */
#define IFX_EVADC_FC_FCRAMP1_FCRCOMPB_MSK (0x3ffu)

/** \brief Offset for Ifx_EVADC_FC_FCRAMP1_Bits.FCRCOMPB */
#define IFX_EVADC_FC_FCRAMP1_FCRCOMPB_OFF (0u)

/** \brief Length for Ifx_EVADC_FC_FCBFL_Bits.BFL */
#define IFX_EVADC_FC_FCBFL_BFL_LEN (1u)

/** \brief Mask for Ifx_EVADC_FC_FCBFL_Bits.BFL */
#define IFX_EVADC_FC_FCBFL_BFL_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_FC_FCBFL_Bits.BFL */
#define IFX_EVADC_FC_FCBFL_BFL_OFF (0u)

/** \brief Length for Ifx_EVADC_FC_FCBFL_Bits.BFA */
#define IFX_EVADC_FC_FCBFL_BFA_LEN (1u)

/** \brief Mask for Ifx_EVADC_FC_FCBFL_Bits.BFA */
#define IFX_EVADC_FC_FCBFL_BFA_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_FC_FCBFL_Bits.BFA */
#define IFX_EVADC_FC_FCBFL_BFA_OFF (4u)

/** \brief Length for Ifx_EVADC_FC_FCBFL_Bits.BFI */
#define IFX_EVADC_FC_FCBFL_BFI_LEN (1u)

/** \brief Mask for Ifx_EVADC_FC_FCBFL_Bits.BFI */
#define IFX_EVADC_FC_FCBFL_BFI_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_FC_FCBFL_Bits.BFI */
#define IFX_EVADC_FC_FCBFL_BFI_OFF (8u)

/** \brief Length for Ifx_EVADC_FC_FCBFL_Bits.BFS */
#define IFX_EVADC_FC_FCBFL_BFS_LEN (2u)

/** \brief Mask for Ifx_EVADC_FC_FCBFL_Bits.BFS */
#define IFX_EVADC_FC_FCBFL_BFS_MSK (0x3u)

/** \brief Offset for Ifx_EVADC_FC_FCBFL_Bits.BFS */
#define IFX_EVADC_FC_FCBFL_BFS_OFF (12u)

/** \brief Length for Ifx_EVADC_FC_FCBFL_Bits.BFM */
#define IFX_EVADC_FC_FCBFL_BFM_LEN (1u)

/** \brief Mask for Ifx_EVADC_FC_FCBFL_Bits.BFM */
#define IFX_EVADC_FC_FCBFL_BFM_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_FC_FCBFL_Bits.BFM */
#define IFX_EVADC_FC_FCBFL_BFM_OFF (16u)

/** \brief Length for Ifx_EVADC_FC_FCBFL_Bits.BFV */
#define IFX_EVADC_FC_FCBFL_BFV_LEN (1u)

/** \brief Mask for Ifx_EVADC_FC_FCBFL_Bits.BFV */
#define IFX_EVADC_FC_FCBFL_BFV_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_FC_FCBFL_Bits.BFV */
#define IFX_EVADC_FC_FCBFL_BFV_OFF (17u)

/** \brief Length for Ifx_EVADC_FC_FCBFL_Bits.BFLNP */
#define IFX_EVADC_FC_FCBFL_BFLNP_LEN (4u)

/** \brief Mask for Ifx_EVADC_FC_FCBFL_Bits.BFLNP */
#define IFX_EVADC_FC_FCBFL_BFLNP_MSK (0xfu)

/** \brief Offset for Ifx_EVADC_FC_FCBFL_Bits.BFLNP */
#define IFX_EVADC_FC_FCBFL_BFLNP_OFF (24u)

/** \brief Length for Ifx_EVADC_FC_FCBFL_Bits.FCR */
#define IFX_EVADC_FC_FCBFL_FCR_LEN (1u)

/** \brief Mask for Ifx_EVADC_FC_FCBFL_Bits.FCR */
#define IFX_EVADC_FC_FCBFL_FCR_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_FC_FCBFL_Bits.FCR */
#define IFX_EVADC_FC_FCBFL_FCR_OFF (28u)

/** \brief Length for Ifx_EVADC_FC_FCBFL_Bits.VF */
#define IFX_EVADC_FC_FCBFL_VF_LEN (1u)

/** \brief Mask for Ifx_EVADC_FC_FCBFL_Bits.VF */
#define IFX_EVADC_FC_FCBFL_VF_MSK (0x1u)

/** \brief Offset for Ifx_EVADC_FC_FCBFL_Bits.VF */
#define IFX_EVADC_FC_FCBFL_VF_OFF (31u)

/** \brief Length for Ifx_EVADC_FC_FCHYST_Bits.DELTAMINUS */
#define IFX_EVADC_FC_FCHYST_DELTAMINUS_LEN (10u)

/** \brief Mask for Ifx_EVADC_FC_FCHYST_Bits.DELTAMINUS */
#define IFX_EVADC_FC_FCHYST_DELTAMINUS_MSK (0x3ffu)

/** \brief Offset for Ifx_EVADC_FC_FCHYST_Bits.DELTAMINUS */
#define IFX_EVADC_FC_FCHYST_DELTAMINUS_OFF (2u)

/** \brief Length for Ifx_EVADC_FC_FCHYST_Bits.DELTAPLUS */
#define IFX_EVADC_FC_FCHYST_DELTAPLUS_LEN (10u)

/** \brief Mask for Ifx_EVADC_FC_FCHYST_Bits.DELTAPLUS */
#define IFX_EVADC_FC_FCHYST_DELTAPLUS_MSK (0x3ffu)

/** \brief Offset for Ifx_EVADC_FC_FCHYST_Bits.DELTAPLUS */
#define IFX_EVADC_FC_FCHYST_DELTAPLUS_OFF (18u)

/** \}  */

/******************************************************************************/

/******************************************************************************/

#endif /* IFXEVADC_BF_H */
